Memory state management for electronic device
In one embodiment a controller comprises logic to determine whether an electronic device is operating in a low power state and in response to a determination that the electronic device is operating in a low power state, implement a memory state management routine which reduces power to at least a section of volatile memory in the memory system. Other embodiments may be described.
1. A computer program product comprising logic instructions stored in a non-transitory computer readable medium which, when executed by a controller, configure the controller to perform operations to manage a memory state of a volatile memory comprising a plurality of direct in-line memory modules (DIMMS), comprising:
determining whether an electronic device comprising a volatile memory and a nonvolatile memory is operating in a low power state; and
in response to a determination that the electronic device is operating in the low power state, determining whether a cache miss rate is below a threshold; and
in response to a determination that the cache miss rate is below the threshold:
identifying one or more least recently used sections of the volatile memory which are in a modified state;
relocating data only from the one or more least recently used sections of a first DIMIM of the volatile memory which are in the modified state to a subset of DIMMs in the volatile memory; and
powering down the first DIMM of the volatile memory.
2. The computer program product of claim 1 , further comprising logic instructions stored in the non-transitory computer readable medium which, when executed by the controller, configure the controller to perform operations comprising:
identifying one or more sections of the volatile memory which are in an invalid state; and
suspending refresh operations to the one or more sections of the volatile memory in an the invalid state.
3. The computer program product of claim 1 , further comprising logic instructions stored in the non-transitory computer readable medium which, when executed by the controller, configure the controller to perform operations comprising:
identifying one or more sections of the volatile memory which are in a modified state;
relocating data from the one or more sections of the volatile memory which are in the modified state; and
powering down the one or more sections of the volatile memory.
4. The computer program product of claim 1 , further comprising logic instructions stored in the non-transitory computer readable medium which, when executed by the controller, configure the controller to perform operations comprising:
in response to the determination that the cache miss rate is not below the threshold:
activating at least one inactive DIMM of the volatile memory.
5. The computer program product of claim 1 , wherein the sections of volatile memory correspond to at least one of a cache line, a memory chip, a memory rank, or a memory bank.
6. The computer program product of claim 1 , further comprising logic instructions stored in the non-transitory computer readable medium which, when executed by the controller, configure the controller to perform operations comprising:
arranging the volatile memory such that read-only pages are located contiguously.
7. A controller comprising logic to:
determine whether an electronic device comprising a volatile memory and a nonvolatile memory comprising a plurality of direct in-line memory modules (DIMMS) is operating in a low power state; and
in response to a determination that the electronic device is operating in the low power state, determine whether a cache miss rate is below a threshold; and
in response to a determination that the cache miss rate is below the threshold:
identify one or more least recently used sections of the volatile memory which are in a modified state;
relocate data only from the one or more least recently used sections of a first DIMIM of the volatile memory which are in the modified state to a subset of DIMMs in the volatile memory; and
power down the first DIMM of the volatile memory.
8. The controller of claim 7 , comprising logic to:
identify one or more sections of volatile memory which are in an invalid state; and
suspend refresh operations to the one or more sections of volatile memory in the invalid state.
9. The controller of claim 7 , further comprising logic to:
in response to a determination that the cache miss rate is not below the threshold:
activate at least one inactive DIMM of the volatile memory.
10. The controller of claim 7 , comprising logic to:
identify one or more sections of the volatile memory which are in a modified state;
relocate data from the one or more sections of the volatile memory which are in the modified state; and
power down the one or more sections of the volatile memory.
11. The controller of claim 7 , wherein the sections of volatile memory correspond to at least one of a cache line, a memory chip, a memory rank, or a memory bank.
12. The controller of claim 7 , comprising logic to:
arrange the volatile memory such that read-only pages are located contiguously.
13. An electronic device, comprising:
a memory system comprising a plurality of direct in-line memory modules (DIMMS); and
a controller comprising logic to:
determine whether an electronic device is operating in a low power state; and
in response to a determination that the electronic device is operating in the low power state, determine whether a cache miss rate is below a threshold; and
in response to a determination that the cache miss rate is below the threshold:
identify one or more least recently used sections of the volatile memory which are in a modified state;
relocate data only from the one or more least recently used sections of a first DIMM of the volatile memory which are in the modified state to a subset of DIMMs in the volatile memory; and
power down the first DIMM of the volatile memory.
14. The electronic device of claim 13 , wherein the controller comprises logic to:
identify one or more sections of the volatile memory which are in an invalid state; and
suspend refresh operations to the one or more sections of the volatile memory in the invalid state.
15. The electronic device of claim 13 , wherein the controller comprises logic to:
identify one or more sections of the volatile memory which are in a modified state;
relocate data from the one or more sections of the volatile memory which are in the modified state; and
power down the one or more sections of the volatile memory.
16. The electronic device of claim 13 , wherein the controller comprises logic to:
in response to a determination that the cache miss rate is not below the threshold:
activate at least one inactive DIMM of the volatile memory.
17. The electronic device of claim 13 , wherein the sections of volatile memory correspond to at least one of a cache line, a memory chip, a memory rank, or a memory bank.
18. The electronic device of claim 13 , wherein the controller comprises logic to:
arrange the volatile memory such that read-only pages are located contiguously.
19. A method to manage a memory system coupled to an electronic device, wherein the memory system comprises a volatile memory and a nonvolatile memory comprising a plurality of direct in-line memory modules (DIMMS), comprising:
determining, in a controller, whether an electronic device is operating in a low power state; and
in response to a determination that the electronic device is operating in the low power state, determining whether a cache miss rate is below a threshold; and
in response to a determination that the cache miss rate is below the threshold:
identifying one or more least recently used sections of a volatile memory which are in a modified state;
relocating data only from the one or more least recently used sections of a first DIMIM of the volatile memory which are in the modified state to a subset of DIMMs in the volatile memory; and
powering down the first DIMM of the volatile memory.
20. The method of claim 19 , further comprising:
identifying one or more sections of the volatile memory which are in an invalid state; and
suspending refresh operations to the one or more sections of the volatile memory in the invalid state.
21. The method of claim 19 , further comprising:
identifying one or more sections of the volatile memory which are in a modified state;
relocating data from the one or more sections of the volatile memory which are in the modified state; and
powering down the one or more sections of the volatile memory module.
22. The method of claim 19 , further comprising:
in response to a determination that the cache miss rate is not below the threshold:
activating at least one inactive DIMM of the volatile memory.
23. The method of claim 19 , wherein the sections of volatile memory correspond to at least one of a cache line, a memory chip, a memory rank, or a memory bank.
24. The method of claim 19 , further comprising:
arranging the volatile memory such that read-only pages are located contiguously.