Semiconductor device and bump formation process
A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump.
1. A semiconductor device, comprising:
a pad region on a semiconductor substrate;
a solder bump overlying and connected to the pad region, the solder bump having a top portion distal the pad region, a bottom portion proximal the pad region, and a sidewall surface between the top portion and the bottom portion, the sidewall surface defining a lateral extent of the solder bump; and
a metal cap layer lining at least a portion of the sidewall surface of the solder bump while exposing the top portion of the solder bump;
wherein:
the solder bump comprises a substantially homogenous material; and
the metal cap layer has a melting temperature greater than a melting temperature of the solder bump.
2. The semiconductor device of claim 1 , wherein the metal cap layer comprises at least one of nickel, palladium, gold, or copper.
3. The semiconductor device of claim 1 , wherein the solder bump comprises a lead-free solder material.
4. The semiconductor device of claim 1 , wherein the metal cap layer is formed on a middle sidewall surface of the solder bump.
5. The semiconductor device of claim 4 , wherein the bottom portion of the solder bump laterally protrudes outside the metal cap layer.
6. The semiconductor device of claim 1 , wherein the metal cap layer is formed on a lower sidewall surface of the solder bump and extends to the bottom portion of the solder bump.
7. The semiconductor device of claim 3 , wherein the solder bump comprises SnAgCu with less than 0.3% Cu by weight.
8. The semiconductor device of claim 1 , wherein the substantially homogenous material comprises a substantially pure metal or a substantially homogenous metal alloy.
9. The semiconductor device of claim 1 , further comprising an under-bump-metallurgy (UBM) layer over the pad region.
10. A packaging assembly, comprising:
a semiconductor substrate;
a package substrate; and
a bump structure disposed between and electrically connecting the semiconductor substrate and the package substrate;
wherein:
the bump structure comprises a solder bump and a metal cap layer covering at least a portion of a lateral sidewall surface of the solder bump proximal the semiconductor substrate;
a top portion of the solder bump proximal the package substrate protrudes toward the package substrate and away from the metal cap layer;
the metal cap layer has a melting temperature greater than a melting temperature of the solder bump; and
the solder bump comprises a substantially homogenous material.
11. The packaging assembly of claim 10 , wherein the metal cap layer comprises at least one of nickel, palladium and gold.
12. The packaging assembly of claim 11 , wherein the metal cap layer comprises copper.
13. The packaging assembly of claim 11 , wherein the solder bump comprises a lead-free solder material.
14. The packaging assembly of claim 11 , wherein the metal cap layer is formed on a middle sidewall surface of the solder bump.
15. The packaging assembly of claim 11 , wherein the metal cap layer is formed on a lower sidewall surface of the solder bump and covers a bottom portion of the solder bump.
16. The packaging assembly of claim 10 , wherein the substantially homogenous material comprises a substantially pure metal or a substantially homogenous metal alloy.
17. A semiconductor device, comprising:
a solder bump overlying a semiconductor substrate, the solder bump comprising a lateral sidewall surface proximal the semiconductor substrate, and a top portion distal the semiconductor substrate, the lateral sidewall surface defining a lateral extent of the solder bump; and
a metal cap layer lining at least the lateral sidewall surface of the solder bump while the top portion of the solder bump is free from the metal cap layer;
wherein:
the solder bump comprises a substantially homogenous material; and
the metal cap layer has a melting temperature greater than a melting temperature of the solder bump.
18. The semiconductor device of claim 17 , wherein the metal cap layer has a thickness in a range from about 0.02 micrometers to about 5 micrometers.
19. The semiconductor device of claim 17 , wherein a bottom portion of the solder bump proximal the semiconductor substrate extends laterally past the metal cap layer.
20. The semiconductor device of claim 17 , wherein the metal cap layer comprises at least one of nickel, palladium, gold, or copper.
21. The semiconductor device of claim 17 , further comprising a pad region disposed between the solder bump and the semiconductor substrate.
22. The semiconductor device of claim 17 , wherein the substantially homogenous material comprises a substantially pure metal or a substantially homogenous metal alloy.