IP Library Granted Patent US 9,455,227
Granted Patent B1
US 9,455,227 · App. 14/935,456 · Granted Sep 27, 2016

Semiconductor device and method for fabricating the same

Inventors: Ching-Wen Hung (Tainan, TW); Jia-Rong Wu (Kaohsiung, TW); Yi-Hui Lee (Taipei, TW); Ying-Cheng Liu (Tainan, TW); Chih-Sen Huang (Tainan, TW); Chun-Hsien Lin (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L23/535H01L21/28088H01L21/76889H01L21/76895H01L29/0653H01L29/66545H01L29/66795H01L29/7851
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Quick Facts
Patent No.
US 9,455,227
App. No.
14/935,456
Granted
Sep 27, 2016
Kind
B1
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Claims (20)

1. A semiconductor device, comprising:

a substrate having a fin-shaped structure thereon;

a first gate structure on the fin-shaped structure;

a first contact plug adjacent to the first gate structure, wherein the first contact plug comprises metal;

a first hard mask on the first contact plug; and

a second hard mask on the first gate structure, wherein the top surfaces of the second hard mask and the first hard mask are coplanar.

2. The semiconductor device of claim 1 , further comprising:

a shallow trench isolation (STI) around the fin-shaped structure;

a second gate structure on the STI;

a first spacer adjacent to the first gate structure and a second spacer adjacent to the second gate structure; and

an interlayer dielectric (ILD) layer adjacent to the second gate structure on the STI.

3. The semiconductor device of claim 2 , further comprising:

a third gate structure on the fin-shaped structure; and

a third spacer adjacent to the third gate structure, wherein the first contact plug contact the first spacer and the third spacer.

4. The semiconductor device of claim 1 , wherein the first hard mask and the second hard mask comprise different material.

5. The semiconductor device of claim 1 , further comprising:

a dielectric layer on the first gate structure; and

a second contact plug in the dielectric layer and the first hard mask and contacting the first contact plug.

6. The semiconductor device of claim 5 , wherein the dielectric layer and the first hard mask comprise same material.

7. The semiconductor device of claim 5 , wherein the second contact plug contacts the first hard mask directly.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2025
From: UNITED MICROELECTRONICS CORP.
To: STELLAR SEMICONDUCTOR JAPAN GK
Reel/Frame 071913/0125 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HUNG, CHING-WEN; WU, JIA-RONG; LEE, YI-HUI; LIU, YING-CHENG; HUANG, CHIH-SEN; LIN, CHUN-HSIEN
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 036985/0403 →
Priority Claims (1)
TW 104132992 A · Oct 7, 2015 · national