Devices, structures, materials and methods for vertical light emitting transistors and light emitting displays
Devices, structures, materials and methods for vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Porous conductive transparent electrodes (such as from nanowires (NW)) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, porous conductive electrodes and relevant substrates and gates are utilized to construct LETs, including singly and doubly gated VPLETs. In addition, printing processes are utilized to deposit layers of one or more of porous conductive electrodes, LEDs, and dielectric materials on various substrates to construct LETs, including singly and doubly gated VPLETs.
1. A vertical light emitting transistor, comprising:
at least one substrate defining a supportive base portion having top and bottom surfaces;
a first conductive electrode disposed on the top surface of the at least one substrate;
at least one capacitor disposed atop a portion of the first conductive electrode, the at least one capacitor comprised of a dielectric layer formed of at least one dielectric material, the at least one dielectric layer having first and second sides in conductive relation to one of either the conductive source or drain electrodes, and a conductive gate electrode;
a second conductive electrode disposed atop a portion of the at least one capacitor;
a light emitting cell comprised of a light emitting layer formed of at least one light emitting material, the light emitting layer disposed in conductive relation atop a portion of the second conductive electrode;
a third conductive electrode disposed atop a portion of the light emitting cell;
wherein the first conductive electrode is a gate electrode, and the second and third conductive electrodes are selected from drain and source electrodes, and wherein the drain and source electrodes are the cathode and anode of the light emitting cell;
at least a second substrate in supportive relation with said third conductive electrode electrode; and
wherein at least the second conductive electrode disposed between the light emitting layer and the dielectric layer is formed of a conductive porous metal material having sufficient open portions to exhibit a surface coverage of no greater than 50%, such that the dielectric layer makes direct contact with the light emitting layer through the open portions of the conductive porous material.
2. The vertical light emitting transistor of claim 1 , wherein the vertical light emitting transistor comprises at least two capacitors and two gate electrodes, a first capacitor having a dielectric layer disposed between the drain electrode and a first gate electrode and a second capacitor disposed between the source electrode and a second gate electrode; and
wherein the drain and source electrodes are conductive porous metal electrodes that have sufficient open portions to exhibit a surface coverage of no greater than 50%, such that both of the dielectric layers make direct contact with the light emitting layer through the open portions of the conductive porous metal electrodes.
3. The vertical light emitting transistor of claim 1 , wherein the light emitting layer is formed of a light emitting material selected from the group consisting of a crystalline semiconductor selected from GaN, GaP, GaAs, AlGaAs, GaAsP, AlGaInP, ZnSe, InGaN and AlN; a semiconductor nanowire selected from Si and GaAs; a quantum wall; an organometallic complex; an Ir organometallic complex; a small organic conjugated molecule; porphyrin; pentacene; and a conjugated polymer selected from PPV, PVK, MEH-PPV, PPF, PFO and PPP.
4. The vertical light emitting transistor of claim 1 , wherein at least one of either or both the gate electrode and the electrode disposed atop the light emitting cell comprise an electrode material selected from graphene sheets, doped Si, ZTO, ITO, Au, Al, Cu, Ni, Mo, Cr, Ag, metal nanowires, metal plate, metal meshes, metal grids, holey copper, holey graphene, conductive polymers, and a low coverage network of a plurality of nanowires.
5. The vertical light emitting transistor of claim 1 , wherein the at least one conductive porous electrode is formed from a plurality of metal nanowires formed into one of the group of a random or patterned network of a plurality of metal nanowires, a nanowire metal mesh, a nanowire grid, and a nanowire network encased within an elastomeric material.
6. The vertical light emitting transistor of claim 5 , wherein the plurality of nanowires are formed from a plurality of metal nanowires selected from Ag, Au and Cu having an aspect ratio of at least 1000.
7. The vertical light emitting transistor of claim 6 , wherein the plurality of metal nanowires have a diameter less than about 200 nm and a length greater than about 1 micron, and having a surface coverage less than 10%, a sheet resistance less than 100 Ω/sq and a transmission greater than 75%.
8. The vertical light emitting transistor of claim 1 , wherein the dielectric material is selected from the group of an oxides selected from SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 ; a nitride; Si 3 N 4 ; an inorganic salts selected from LiF, CsF, BaTiO 3 , and SrTiO 3 ; a dielectric polymer selected from PMMA, Teflon, CYTOP, and Nafion; and an ionic gel formed from the combination of a dielectric polymer and an ionic liquid.
9. The vertical light emitting transistor of claim 1 , further comprising at least one additional light emitting enhancement layer selected from the group consisting of electron injection dipole layers, transportation dipole layers, conjugate polyelectrolyte layers, and hole injection layers.
10. The vertical light emitting transistor of claim 1 , wherein the at least one substrate is selected from the group consisting of flexible plastics, Si wafer, glass, sapphire, and ITO.
11. A vertical light emitting display comprising a plurality of pixels comprising a plurality of vertical light emitting transistors electronically coupled into addressing electrode lines, each vertical light emitting transistor comprising:
at least one substrate defining a supportive base portion having top and bottom surfaces;
a first conductive electrode disposed on the top surface of the at least one substrate;
at least one capacitor disposed atop a portion of the first conductive electrode, the at least one capacitor comprised of a dielectric layer formed of at least one dielectric material, the at least one dielectric layer having first and second sides in conductive relation to one of either the conductive source or drain electrodes, and a conductive gate electrode;
a second conductive electrode disposed atop a portion of the at least one capacitor;
a light emitting cell comprised of a light emitting layer formed of at least one light emitting material, the light emitting layer disposed in conductive relation atop at least a portion of the second conductive electrode;
a third conductive electrode disposed atop a portion of the light emitting cell;
wherein the first conductive electrode is a gate electrode, and the second and third conductive electrode are selected from drain and source electrodes, and wherein the drain and source electrodes are the cathode and anode of the light emitting cell;
at least a second substrate in supportive relation with said third conductive electrode electrode; and
wherein at least the second conductive electrode disposed between the light emitting layer and the dielectric layer is formed of a conductive porous metal material having sufficient open portions to exhibit a surface coverage of no greater than 50%, such that the dielectric layer makes direct contact with the light emitting layer through the open portions of the conductive porous electrode;
wherein the light emitting layers emit one of either a single color or a plurality of colors; and
wherein each pixel is formed of at least a first transistor configured for switching and at least a second transistor configured for scribing.
12. The vertical light emitting display of claim 11 , wherein each of the vertical light emitting transistors comprises at least two capacitors and two gate electrodes, a first capacitor having a dielectric layer disposed between the drain electrode and a first gate electrode and a second capacitor disposed between the source electrode and a second gate electrode, such that each pixel is formed of a single transistor configured for both switching and scribing; and
wherein the drain and source electrodes are conductive porous metal electrodes that have sufficient open portions to exhibit a surface coverage of no greater than 50%, such that both of the dielectric layers make direct contact with the light emitting layer through the open portions of the conductive porous metal electrodes.
13. The vertical light emitting display of claim 11 , wherein:
the light emitting layer is formed of a light emitting material selected from the group consisting of a crystalline semiconductor selected from GaN, GaP, GaAs, AlGaAs, GaAsP, AlGaInP, ZnSe, InGaN and AlN; a semiconductor nanowire selected from Si and GaAs; a quantum wall; an organometallic complex; an Ir organometallic complex; a small organic conjugated molecule; porphyrin; pentacene; and a conjugated polymer selected from PPV, PVK, MEH-PPV, PPF, PFO and PPP;
the dielectric material is selected from the group of an oxides selected from SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 ; a nitride; Si 3 N 4 ; an inorganic salts selected from LiF, CsF, BaTiO 3 , and SrTiO 3 ; a dielectric polymer selected from PMMA, Teflon, CYTOP, and Nafion; and an ionic gel formed from the combination of a dielectric polymer and an ionic liquid;
the substrates are selected from the group consisting of flexible plastics, Si wafer, glass, sapphire, and ITO;
at least the gate electrodes comprise an electrode material selected from graphene sheets, doped Si, ZTO, ITO, Au, Al, Cu, Ni, Mo, Cr, Ag, metal nanowires, metal plate, metal meshes, metal grids, holey copper, holey graphene, conductive polymers, and a low coverage network of a plurality of nanowires;
wherein the at least one conductive porous electrode is formed from a plurality of metal nanowires formed into one of the group of a random or patterned network of a plurality of metal nanowires, a nanowire metal mesh, a nanowire grid, and a nanowire network encased within an elastomeric material;
wherein the plurality of nanowires are formed from a plurality of metal nanowires selected from Ag, Au and Cu having a diameter less than about 200 nm and a length greater than about 1 micron, and having a surface coverage less than 10%, a sheet resistance less than 15 Ω/sq and a transmission greater than 75%; and
wherein each of the electrode layers are formed such that at least a portion of the upper surface of the electrode layer remains uncovered by the layer disposed thereon.