IP Library Granted Patent US 9,460,957
Granted Patent B2
US 9,460,957 · App. 14/021,608 · Granted Oct 4, 2016

Method and structure for nitrogen-doped shallow-trench isolation dielectric

Inventors: Shing Long Lee (Hsinchu, TW); Yi-Chieh Wang (Taipei, TW); Chung-Han Lin (Jhubei, TW); Kuang-Jung Peng (Hsinchu, TW); Yun Chang (Hsinchu, TW); Shou-Wen Kuo (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/76237H01L21/02126H01L21/02271
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Quick Facts
Patent No.
US 9,460,957
App. No.
14/021,608
Granted
Oct 4, 2016
Kind
B2
Abstract

An isolation feature with a nitrogen-doped fill dielectric and a method of forming the isolation feature are disclosed. In an exemplary embodiment, the method of forming the isolation feature comprises receiving a substrate having a top surface. A recess is etched in the substrate, the recess extending from the top surface into the substrate. A dielectric is deposited within the recess such that the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process. Accordingly, the deposited dielectric includes a nitrogen-doped dielectric. The deposited dielectric may include a nitrogen-doped silicon oxide. In some embodiments, the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess. In further embodiments, a liner material is deposited within the recess prior to the depositing of the dielectric within the recess.

Claims (33)

1. A method of forming an isolation feature, the method comprising:

receiving a substrate having a top surface;

etching a recess in the substrate, the recess extending from the top surface into the substrate; and

depositing a dielectric within the recess,

wherein the depositing of the dielectric includes introducing nitrogen during a chemical vapor deposition process,

whereby the deposited dielectric includes a nitrogen-doped dielectric, and

wherein the introducing of nitrogen during the chemical vapor deposition process introduces gas at a flow rate ratio for nitrogen gas (N 2 ) to oxygen gas (O 2 ) of between about 1:100 and about 1:22.

2. The method of claim 1 , wherein the deposited dielectric includes a nitrogen-doped silicon oxide.

3. The method of claim 1 , wherein the depositing of the dielectric disposes the nitrogen-doped dielectric in contact with a surface of the recess.

4. The method of claim 1 further comprising depositing a liner material within the recess prior to the depositing of the dielectric within the recess.

5. The method of claim 4 , wherein the liner material includes a semiconductor oxide.

6. The method of claim 1 , wherein the introducing of nitrogen during the chemical vapor deposition process introduces the nitrogen gas (N 2 ) at a flow rate between about 2 and about 10 standard cubic centimeters per minute.

7. The method of claim 6 , wherein the depositing of the dielectric further includes introducing the oxygen gas (O 2 ) at a flow rate between about 220 and about 290 standard cubic centimeters per minute.

8. The method of claim 1 , wherein the depositing of the dielectric further includes a plurality of iterations of a chemical vapor deposition process, and wherein the introducing of the nitrogen during the chemical vapor deposition process introduces the nitrogen during each of the plurality of iterations.

9. A method of fabricating an integrated circuit, the method comprising:

receiving a substrate having a first circuit device and a second circuit device disposed upon the substrate;

etching a trench extending into the substrate, the trench disposed between the first circuit device and the second circuit device; and

depositing a nitrogen-doped dielectric within the trench,

wherein the depositing of the nitrogen-doped dielectric includes introducing nitrogen during the depositing, and

wherein the introducing of nitrogen during the depositing introduces gas at a flow rate ratio for nitrogen gas (N 2 ) to oxygen gas (O 2 ) of between about 1:100 and about 1:22.

10. The method of claim 9 , wherein the deposited nitrogen-doped dielectric includes a nitrogen-doped silicon oxide dielectric.

11. The method of claim 9 , wherein the depositing disposes the nitrogen-doped dielectric in contact with a semiconductor material of the substrate within the trench.

12. The method of claim 9 further comprising depositing a liner material within the trench prior to the depositing the nitrogen-doped dielectric.

13. The method of claim 12 , wherein the liner material includes a semiconductor oxide.

14. The method of claim 9 , wherein the introducing of the nitrogen during the depositing introduces the nitrogen gas (N 2 ) at a flow rate between about 2 and about 10 standard cubic centimeters per minute.

15. The method of claim 14 , wherein the depositing of the nitrogen-doped dielectric further includes introducing the oxygen gas (O 2 ) at a flow rate between about 220 and about 290 standard cubic centimeters per minute.

16. A method comprising:

receiving a substrate having an isolation region defined thereupon, wherein the isolation region includes a trench extending into the substrate;

forming an isolation feature within the isolation region, wherein the forming of the isolation feature includes:

depositing a liner material on the substrate within the trench; and

depositing a fill dielectric on the liner material within the trench such that the fill dielectric contains between about 0.4 atomic percent and about 2.0 atomic percent nitrogen, wherein the depositing of the fill dielectric includes performing a chemical vapor deposition process using a nitrogen to oxygen flow ratio of between about 1:100 and about 1:22.

17. The method of claim 16 , wherein the depositing of the liner material is configured to deposit the liner material to include a semiconductor oxide.

18. The method of claim 4 , wherein the liner material includes a semiconductor nitride.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2015
From: LEE, SHING LONG; WANG, YI-CHIEH; LIN, CHUNG-HAN; PENG, KUANG-JUNG; CHANG, YUN; KUO, SHOU-WEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 034654/0586 →
Continuity (2)
Provisional Application 61778254 · Mar 12, 2013
Related Publication 20140264720A1 · Sep 18, 2014