Vertical memory devices and methods of manufacturing the same
A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.
1. A method of manufacturing a vertical memory device, the method comprising:
forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon;
forming channel holes through the insulating interlayers and the sacrificial layers;
forming channels in the channel holes;
etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings;
removing the sacrificial layers to form gaps between the insulating interlayers; and
forming gate lines in the gaps.
2. The method as claimed in claim 1 , wherein the channels and gate lines are formed on a cell region of the substrate, a dummy region of the substrate being defined between two adjacent cell regions.
3. The method as claimed in claim 2 , wherein removing the sacrificial layers includes leaving portions of the sacrificial layers on the dummy region, such that the portions of the sacrificial layers on the dummy region define supporting patterns.
4. The method as claimed in claim 1 , further comprising forming a dielectric layer structure between a sidewall of the channel hole and the channel, the gate lines surrounding an outer sidewall of the dielectric layer structure.
5. The method as claimed in claim 1 , further comprising forming a semiconductor pattern on a top surface of the substrate exposed by the channel hole, before the forming the channel, the channel being formed on a top surface of the semiconductor pattern.
6. The method as claimed in claim 5 , wherein forming the gate lines includes forming a ground selection line (GSL), at least one word line, and a string selection line (SSL) sequentially stacked from the top surface of the substrate, the GSL surrounding an outer sidewall of the semiconductor pattern.
7. The method as claimed in claim 6 , further comprising removing a lateral portion of the semiconductor pattern together with the sacrificial layers to form a first recess, the GSL being inserted in the first recess.
8. The method as claimed in claim 1 , further comprising providing impurities through the opening to form an impurity region at an upper portion of the substrate, the impurity region being a common source line (CSL).
9. The method as claimed in claim 8 , further comprising partially removing the upper portion of the substrate together with the sacrificial layers to form a second recess, the impurities being implanted through the second recess.
10. The method as claimed in claim 1 , further comprising forming barrier oxide layer patterns at lateral portions of the sacrificial layers exposed by the channel hole.
11. The method as claimed in claim 1 , wherein:
removing the sacrificial layers includes leaving portions of the sacrificial layers in the gaps to form preliminary gate lines; and
forming the gate lines includes:
forming a metal layer to fill remaining portions of the gaps, and
reacting the metal layer and the preliminary gate lines to form a metal silicide pattern in each gap.
12. The method as claimed in claim 1 , wherein:
the insulating interlayer is formed using silicon oxide; and
removing the sacrificial layers is performed by a gas phase etching process using a chlorine gas or a wet etching process using an etchant solution that contains a hydroxyl group.
13. The method as claimed in claim 1 , wherein removing the sacrificial layers includes selectively removing only the sacrificial layers among the sacrificial layers and the insulating interlayers, such that substantially no portions of the insulating interlayers are removed.
14. A method of manufacturing a vertical memory device, the method comprising:
stacking a plurality of alternating insulating interlayers and sacrificial layers on a substrate along a vertical direction with respect to a top surface of a substrate, the insulating interlayers including an oxide-based material, and the sacrificial layers including polysilicon or amorphous silicon;
forming channels through the plurality of insulating interlayers and sacrificial layers, the channels extending along the vertical direction;
forming openings between adjacent channels, the openings extending along the vertical direction;
removing the sacrificial layers through the openings, such that gaps are defined between insulating interlayers adjacent to each other along the vertical direction; and
forming gate lines in the gaps.
15. The method as claimed in claim 14 , wherein removing the sacrificial layers includes removing only the sacrificial layers among the sacrificial layers and the insulating interlayers, such that substantially no portions of the insulating interlayers are removed.
16. The method as claimed in claim 14 , wherein removing the sacrificial layers includes leaving portions of the sacrificial layers in a dummy region.
17. The method as claimed in claim 14 , wherein:
stacking the plurality of alternating insulating interlayers and sacrificial layers includes alternating silicon oxide insulating interlayers and polysilicon sacrificial layers; and
removing the sacrificial layers includes etching using a chlorine gas or a solution containing a hydroxyl group.