IP Library › Granted Patent US 9,461,073
Granted Patent B2
US 9,461,073 · App. 14/429,870 · Granted Oct 4, 2016

Array substrate, manufacturing method thereof, and display device

Inventors: Zhiqiang Xu (Beijing, CN); Heecheol Kim (Beijing, CN); Chao Xu (Beijing, CN)
Assignee: Boe Technology Group Co., Ltd.
H01L27/124G02F1/1368G02F1/133707G02F1/134363H01L27/12H01L27/1259G02F2001/134372
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Quick Facts
Patent No.
US 9,461,073
App. No.
14/429,870
Granted
Oct 4, 2016
Kind
B2
Abstract

The embodiments of the invention provide an array substrate, a method for manufacturing the same and a display device, relate to the field of display technology, and can reduce the color cast phenomenon of the display device, and improve the display effect. The array substrate comprises a plurality of pixel units which are arranged in an array, each of the pixel units comprises a plurality of sub-pixel units, the width of each of the sub-pixel units is equal, each of the sub-pixel units corresponds to one first electrode, the first electrode comprises a plurality of strip-shaped structures which are arranged at an equal interval, and intervals of the strip-shaped structures of the first electrodes corresponding to different sub-pixel units in each of the pixel units are not completely equal; any of the sub-pixel units meets Q·W+(Q−1)D<A, wherein A is the width of the sub-pixel units, Q is the number of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, D is the interval of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, and W is the width of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units.

Claims (37)

1. An array substrate comprising: a plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixel units, the width of each of the sub-pixel units being equal, each of the sub-pixel units corresponding to one first electrode, each of the first electrodes comprising a plurality of strip-shaped structures arranged at an equal electrode gap, wherein

electrode gaps of the strip-shaped structures of the first electrodes corresponding to different sub-pixel units in each of the pixel units are not completely equal; and

any of the sub-pixel units meets Q·W+(Q−1)D<A, wherein A is the width of the sub-pixel units, Q is the number of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, D is the electrode gap of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, and W is the electrode width of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units;

each of the pixel units comprises three sub-pixel units, wherein the three sub-pixel units comprise a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit; and the number Q of the strip-shaped structures of the first electrode corresponding to each of the sub-pixel units is 3;

wherein the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the red sub-pixel unit is d 1 ;

the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the green sub-pixel unit is d 2 ;

the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the blue sub-pixel unit is d 3 ; and

d 1 , d 2 and d 3 satisfy d 1 =d 2 <d 3 .

2. The array substrate as claimed in claim 1 , wherein d 1 is 4 μm, d 2 is 4 μm, and d 3 is 6 μm.

3. The array substrate as claimed in claim 2 , wherein d 1 is 4.5 μm, d 2 is 4.5 μm, and d 3 is 6.5 μm.

4. A display device comprising: an array substrate, the array substrate comprising a plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixel units, the width of each of the sub-pixel units being equal, each of the sub-pixel units corresponding to one first electrode, each of the first electrodes comprising a plurality of strip-shaped structures arranged at an equal electrode gap, wherein

electrode gaps of the strip-shaped structures of the first electrodes corresponding to different sub-pixel units in each of the pixel units are not completely equal; and

any of the sub-pixel units meets Q·W+(Q−1)D<A, wherein A is the width of the sub-pixel units, Q is the number of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, D is the electrode gap of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, and W is the electrode width of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units;

each of the pixel units comprises three sub-pixel units, wherein the three sub-pixel units comprise a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit and the number Q of the strip-shaped structures of the first electrode corresponding to each of the sub-pixel units is 3;

wherein the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the red sub-pixel unit is d 1 ;

the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the green sub-pixel unit is d 2 ;

the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the blue sub-pixel unit is d 3 ; and

d 1 , d 2 and d 3 satisfy d 1 =d 2 <d 3 .

5. The display device as claimed in claim 4 , wherein d 1 is 4 μm, d 2 is 4 μm, and d 3 is 6 μm.

6. The display device as claimed in claim 4 , wherein d 1 is 4.5 μm, d 2 is 4.5 μm, and d 3 is 6.5 μm.

7. A method for manufacturing an array substrate, the array substrate comprising a plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixel units, the width of each of the sub-pixel units being equal, each of the sub-pixel units corresponding to one first electrode, each of the first electrodes comprising a plurality of strip-shaped structures arranged at an equal electrode gap, wherein the method comprises:

for any one of the sub-pixel units, depositing a first transparent conductive thin film layer on a substrate on which a thin film transistor TFT structure is formed and forming the first electrode through a single patterning process;

wherein electrode gaps of the strip-shaped structures of the first electrodes corresponding to different sub-pixel units in each of the pixel units are not completely equal; and

any of the sub-pixel units meets Q·W+(Q−1)D<A, wherein A is the width of the sub-pixel units, Q is the number of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, D is the electrode gap of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units, and W is the electrode width of the strip-shaped structures of the first electrodes corresponding to the sub-pixel units;

each of the pixel units comprises three sub-pixel units, wherein the three sub-pixel units comprise a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit and the number Q of the strip-shaped structures of the first electrode corresponding to each of the sub-pixel units is 3;

wherein the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the red sub-pixel unit is d 1 ;

the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the green sub-pixel unit is d 2 ;

the electrode gap interval of the strip-shaped structures of the first electrode corresponding to the blue sub-pixel unit is d 3 ; and

d 1 , d 2 and d 3 satisfy d 1 =d 2 <d 3 .

8. The method as claimed in claim 7 , wherein the step of depositing a first transparent conductive thin film layer on a substrate having a thin film transistor TFT structure formed thereon and forming the first electrode through a single patterning process comprises:

depositing a second transparent conductive thin film layer on the substrate having a thin film transistor TFT structure formed thereon and forming a second electrode through a single patterning process;

forming a passivation layer on the substrate having the second electrode formed thereon; and

depositing the first transparent conductive thin film layer on the substrate having the passivation layer formed thereon and forming the first electrode through a single patterning process.

9. The method as claimed in claim 7 , wherein

d 1 is 4 μm, d 2 is 4 μm, and d 3 is 6 μm.

10. The method as claimed in claim 7 , wherein

d 1 is 4.5 μm, d 2 is 4.5 μm, and d 3 is 6.5 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2015
From: XU, ZHIQIANG; KIM, HEECHEOL; XU, CHAO
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 035251/0057 →
Priority Claims (1)
CN 2014 1 0032264 · Jan 23, 2014 · national
Continuity (1)
Related Publication 20160027798A1 · Jan 28, 2016