Memory management unit that applies rules based on privilege identifier
A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request.
1. A method of memory management comprising the steps of:
organizing a memory as a plurality of memory segments addressable within a logical address space of the memory,
controlling access to the memory by requests originated by a plurality of requestors based on a privilege identifier (PRIVID) accompanying each request for access, including
storing access permission data of memory segments in a plurality of banks of segment registers, each bank of segment registers including a plurality of segment registers, each segment register corresponding to one of the memory segments of the memory,
selecting one of the banks of segment registers corresponding to a received privilege identifier (PRIVID) of a request for access,
comparing the privilege identifier (PRIVID) and address of a request for access to the selected bank of segment registers to the permission data stored in a segment register of the selected bank of segment registers corresponding to the memory segment addressed by the address of the request for access, and
granting access if comparing step indicates a valid request for access.
2. The method of claim 1 , further comprising the steps of:
classifying a plurality of requestors as Masters, each Master requestor having an assigned privilege identifier (PRIVID) identifying memory accesses permitted by that Master requestor; and
classifying at least one requestor classified as a deputy Master, each deputy Master requestor operating under control of one of the plurality of Master requestors and supplying a privilege identifier (PRIVID) of the controlling Master requestor when making an access request.
3. The method of claim 2 , wherein:
the plurality of master requestors each include a central processing unit (CPU), each central processing unit (CPU) master requestor performing data processing operations including memory accesses under program control.
4. The method of claim 2 , wherein:
the at least one deputy master requestors each include a direct memory access (DMA) unit, each direct memory access (DMA) unit performing access to memory under control of a Master requestor.