IP Library › Granted Patent US 9,466,611
Granted Patent B2
US 9,466,611 · App. 14/812,376 · Granted Oct 11, 2016

Integrated circuit device and method for manufacturing the same

Inventors: Yosuke Komori (Yokohama, JP); Yasuyoshi Hyodo (Ota, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/11582H01L21/28282H01L21/32053H01L21/32134H01L27/11551H01L27/11556
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Quick Facts
Patent No.
US 9,466,611
App. No.
14/812,376
Granted
Oct 11, 2016
Kind
B2
Abstract

An integrated circuit device according to one embodiment includes a plurality of first electrode films stacked spaced from each other, a plurality of second electrode films stacked spaced from each other on the plurality of first electrode films and extending in one direction, a semiconductor pillar penetrating the first electrode films and the second electrode films, a memory film provided between the first electrode films and the semiconductor pillar and capable of storing charge, a gate insulating film provided between the second electrode films and the semiconductor pillar, and a spacer film electrically connecting width-direction edges of the plurality of second electrode films to each other.

Claims (16)

1. An integrated circuit device comprising:

a plurality of first electrode films stacked spaced from each other;

a plurality of second electrode films stacked spaced from each other, on the plurality of first electrode films, and extending in one direction;

a semiconductor pillar penetrating the first electrode films and the second electrode films;

a memory film provided between the first electrode films and the semiconductor pillar and capable of storing charge;

a gate insulating film provided between the second electrode films and the semiconductor pillar; and

a spacer film electrically connecting width-direction edges of the plurality of second electrode films to each other.

2. The device according to claim 1 , wherein the spacer film extends along a plane including the one direction and a stacking direction of the plurality of second electrode films.

3. The device according to claim 1 , wherein the spacer film connects respective ones of both width-direction edges of the plurality of second electrode films to each other.

4. The device according to claim 1 , further comprising a via penetrating the plurality of second electrode films and connecting the plurality of second electrode films to each other.

5. The device according to claim 1 , wherein the spacer film contains metal silicide.

6. The device according to claim 1 , wherein the spacer film is conductive and contains silicon.

7. The device according to claim 1 , further comprising another spacer film whose composition is different from a composition of the spacer film.

8. The device according to claim 7 , wherein the another spacer film is insulative.

9. The device according to claim 8 , wherein the another spacer film contains aluminum oxide.

10. The device according to claim 9 , wherein the spacer film is conductive and contains silicon.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 29, 2015
From: KOMORI, YOSUKE; HYODO, YASUYOSHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 036209/0220 →
Priority Claims (1)
JP 2014-187561 · Sep 16, 2014 · national
Continuity (1)
Related Publication 20160079270A1 · Mar 17, 2016