Functional ASIC verification using initialization microcode sequence

1. A method of performing wafer-level testing during production of a register-programmable integrated circuit, the method comprising:

generating a microcode instruction by simulating a data exchange between a simulated central electronic complex and a simulation of the register-programmable integrated circuit, wherein the microcode instruction includes at least one code element configured for execution by an initializing processor to initialize the register-programmable integrated circuit after production;

transforming, using a computing device, the microcode instruction and corresponding data from an initializing processor format into tester-formatted data, wherein transforming the microcode instruction includes:

generating, using the microcode instruction, one or more cache-inhibited load/store (CILS) trace entries, and

translating the one or more CILS trace entries into a microcode sequence within the tester-formatted data;

applying, using a tester device coupled with the computing device, the tester-formatted data to the register-programmable integrated circuit; and

verifying, after applying the tester-formatted data to the register-programmable integrated circuit, the function of the integrated circuit based on a global error indicator included in the register-programmable integrated circuit.

2. The method of claim 1 , wherein the applying the tester-formatted data to the register-programmable integrated circuit on the wafer includes at least one of writing the data to the register-programmable integrated circuit and reading other data from the register-programmable integrated circuit.

3. The method of claim 1 , wherein the simulation of the register-programmable integrated circuit is performed using a high-level design language simulator or a hardware design language simulator.

4. The method of claim 1 , wherein the tester-formatted data are data for a very large scale integration (VLSI) application specific integrated circuit (ASIC) tester.

5. The method of claim 1 , wherein the central electronic complex includes a central processor of a mainframe computer.

6. The method of claim 1 , wherein the microcode instruction includes at least one of a read instruction and a write instruction for the register-programmable integrated circuit.

7. The method of claim 1 , wherein the microcode instruction does not include an artificial code pattern and does not include a pseudo-random pattern.

8. The method of claim 1 , wherein translating the one or more CILS trace entries is performed using an application programming interface (API) for the tester device.

9. The method of claim 1 , wherein the tester-formatted data is transmitted as a vector pattern to the register-programmable integrated circuit.

10. The method of claim 1 , further comprising:

determining, based on the microcode instruction, whether to generate any additional CILS trace entries for the microcode sequence.

11. The method of claim 1 , further comprising:

translating a register address included within the microcode instruction; and

including the translated register address in a tester translation table,

wherein the tester-formatted data applied to the register-programmable integrated circuit includes the tester translation table.

12. The method of claim 11 , further comprising:

receiving, in response to application of the tester-formatted data to the register-programmable integrated circuit, an test-data-out bit array; and

determining whether the bit array includes any uninitialized bits.

13. The method of claim 12 , wherein the bit array is determined to not include any uninitialized bits, and further comprising translating the bit array into a hex format for subsequent access.

14. The method of claim 11 , wherein the tester translation table is provided in a format defined by the Joint Test Action Group (JTAG).

15. A system configured to perform wafer-level testing during production of a register-programmable integrated circuit, the system comprising:

a simulation device configured to generate a microcode instruction by simulating a data exchange between a simulated central electronic complex and a simulation of the register-programmable integrated circuit, wherein the microcode instruction includes at least one code element configured for execution by an initializing processor to initialize the register-programmable integrated circuit after production;

a computing device including a transforming unit configured to transform the microcode instruction and corresponding data from an initializing processor format into tester-formatted data, wherein transforming the microcode instruction includes:

generating, using the microcode instruction, one or more cache-inhibited load/store (CILS) trace entries, and

translating the one or more CILS trace entries into a microcode sequence within the tester-formatted data; and

an applying unit configured to apply the tester-formatted data to the register-programmable integrated circuit,

wherein the computing device is further configured to verify, after applying the tester-formatted data to the register-programmable integrated circuit, the function of the register-programmable integrated circuit based on a global error indicator included in the register-programmable integrated circuit.

16. The system of claim 15 , wherein the applying unit is included in a tester device separate from the computing device.

17. The system of claim 15 , wherein the simulation device is a separate device from the computing device that includes the transforming unit.

18. A computer program product to perform wafer-level testing during production of a register-programmable integrated circuit, the computer program product comprising:

a non-transitory computer-readable medium having computer-readable code embodied therewith, the computer-readable code executable by one or more computer processors to:

generate a microcode instruction by simulating a data exchange between a simulated central electronic complex and a simulation of the register-programmable integrated circuit, wherein the microcode instruction includes at least one code element configured for execution by an initializing processor to initialize the register-programmable integrated circuit after production;

transform, using at least one of the computer processors, the microcode instruction and corresponding data from an initializing processor format into tester-formatted data, wherein transforming the microcode instruction includes:

generating, using the microcode instruction, one or more cache-inhibited load/store (CILS) trace entries, and

translating the one or more CILS trace entries into a microcode sequence within the tester-formatted data;

apply, using a tester device coupled with at least one of the computer processors, the tester-formatted data to the register-programmable integrated circuit; and

verify, after applying the tester-formatted data to the register-programmable integrated circuit, the function of the register-programmable integrated circuit based on a global error indicator included in the register-programmable integrated circuit.

19. The computer program product of claim 18 , wherein the generated microcode instruction does not include an artificial code pattern and does not include a pseudo-random pattern.