Method and apparatus for implementing a heterogeneous memory subsystem

1. A processor comprising:

memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and

dynamic remapping logic to

swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed, and

perform chunk-restricted remapping in which a particular chunk is only permitted to be stored in one or more specific regions within the first memory and one or more specific regions in the second memory.

2. The processor as in claim 1 wherein the first set of memory access characteristics comprise higher performance characteristics than the second set of memory access characteristics and wherein the dynamic remapping logic is to allocate memory chunks to the first memory which are accessed relatively more frequently than the memory chunks allocated the second memory.

3. The processor as in claim 2 wherein the first and second sets of memory access characteristics include a memory access latency value.

4. The processor as in claim 2 wherein the first and second sets of memory access characteristics include a memory access bandwidth.

5. The processor as in claim 1 wherein the first memory and the second memory are both dynamic random access (DRAM) memory.

6. The processor as in claim 1 wherein the first memory is on a common die with the processor and the second memory is off-die.

7. The processor as in claim 1 wherein each memory chunk comprises a 2KB region of memory.

8. The processor as in claim 1 wherein the dynamic remapping logic is to dynamically update the memory mapping logic to cause the memory chunks to be swapped between the first and second memories based, at least in part, on the detected frequency with which the memory chunks are accessed.

9. The processor as in claim 1 wherein the memory mapping logic comprises a chunk remapping table (CRT), wherein each entry in the CRT is to specify one or more regions within the fast memory and one or more regions in the slow memory.

10. The processor as in claim 9 wherein the memory mapping logic comprises a chunk remapping cache for caching frequently accessed chunk mappings.

11. The processor as in claim 10 further comprising:

at least one competing counter to be incremented when a first memory chunk within an entry is accessed and to be decremented when a second chunk within the entry is accessed, wherein the dynamic remapping logic determines whether to swap the first chunk with the second chunk based on a current value of the competing counter.

12. A method comprising:

subdividing a system memory space into a plurality of memory chunks;

mapping the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and

dynamically remapping to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed, and to perform chunk-restricted remapping in which a particular chunk is only permitted to be stored in one or more specific regions within the first memory and one or more specific regions in the second memory.

13. The method as in claim 12 wherein the first set of memory access characteristics comprise higher performance characteristics than the second set of memory access characteristics and wherein the dynamic remapping is performed to allocate memory chunks to the first memory which are accessed relatively more frequently than the memory chunks allocated the second memory.

14. The method as in claim 13 wherein the first and second sets of memory access characteristics include a memory access latency value.

15. The method as in claim 13 wherein the first and second sets of memory access characteristics include a memory access bandwidth.

16. The method as in claim 12 wherein the first memory and the second memory are both dynamic random access (DRAM) memory.

17. The method as in claim 12 wherein the first memory is on a common die with the processor and the second memory is off-die.

18. The method as in claim 12 wherein each memory chunk comprises a 2KB region of memory.

19. The method as in claim 12 wherein the dynamic remapping is performed to cause the memory chunks to be swapped between the first and second memories based, at least in part, on the detected frequency with which the memory chunks are accessed.

20. The method as in claim 12 wherein mapping the memory chunks comprises accessing a chunk remapping table (CRT), wherein each entry in the CRT is to specify one or more regions within the fast memory and one or more regions in the slow memory.

21. The method as in claim 20 further comprising:

caching a subset of the entries which are accessed more frequently relative to other entries within a chunk remapping cache (CRC).

22. The method as in claim 21 further comprising:

incrementing a competing counter when a first memory chunk within an entry is accessed and decrementing the competing counter when a second chunk within the entry is accessed, wherein the dynamic remapping determines whether to swap the first chunk with the second chunk based on a current value of the competing counter.