IP Library Granted Patent US 9,474,162
Granted Patent B2
US 9,474,162 · App. 14/151,828 · Granted Oct 18, 2016

Circuit substrate and method of manufacturing same

Inventors: Chee Seng Foong (Sg. Buloh, MY); Lan Chu Tan (Singapore, SG)
Assignee: FREESCALE SEMIOCNDUCTOR, INC.
H05K3/007H05K1/097H05K2203/107
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,474,162
App. No.
14/151,828
Granted
Oct 18, 2016
Kind
B2
Abstract

A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

Claims (26)

1. A method of manufacturing a circuit interconnecting substrate, the method comprising:

depositing a first layer of metallic powder on top of at least one region of a carrier;

forming a first layer of electrically conductive traces from the first layer of metallic powder;

depositing a second layer of metallic powder onto at least one region of the first layer of electrically conductive traces;

forming a second layer of electrically conductive traces from the second layer of metallic powder, each trace of the second layer of electrically conductive traces being electrically coupled to at least one trace of the first layer of electrically conductive traces;

depositing an insulating material onto the carrier, wherein the insulating material forms an insulating substrate that supports the traces; and

depositing a third layer of metallic powder onto at least one region of the second layer of electrically conductive traces; and

forming a third layer of electrically conductive traces from the third layer of metallic powder, each third layer of electrically conductive traces being electrically coupled to at least one of the second layer of electrically conductive traces,

wherein after forming the third layer of electrically conductive traces, removing regions of the metallic powder that do not form the electrically conductive traces.

2. The method of claim 1 , wherein the first layer of metallic powder is deposited directly onto the at least one region of the carrier.

3. The method of claim 1 , wherein forming the first and second layers of electrically conductive traces is performed by selective laser sintering of the metallic powder.

4. The method of claim 1 , wherein forming the first and second layers of electrically conductive traces is performed by a selective laser melting and solidifying of the metallic powder.

5. The method of claim 1 , wherein the depositing of the insulating material is performed after removing the regions of the metallic powder.

6. The method of claim 1 , wherein the insulating substrate forms a sheet with a first side and a second side and wherein the first layer of electrically conductive traces is accessible from the first side and the third layer of electrically conductive traces is accessible from the second side.

7. The method of claim 1 , wherein after forming the first layer of electrically conductive traces, removing regions of the metallic powder that do not form the first layer of electrically conductive traces.

8. A circuit interconnecting substrate manufactured by a method comprising:

depositing a first layer of metallic powder on top of at least one region of a carrier;

forming a first layer of electrically conductive traces from the first layer of metallic powder;

depositing a second layer of metallic powder onto at least one region of the first layer of electrically conductive traces;

forming a second layer of electrically conductive traces from the second layer of metallic powder, each trace of the second layer of electrically conductive traces being electrically coupled to at least one trace of the first layer of electrically conductive traces;

depositing a third layer of metallic powder onto at least one region of the second layer of electrically conductive traces; and

forming a third layer of electrically conductive traces from the third layer of metallic powder, each trace of the third layer of electrically conductive traces being electrically coupled to at least one trace of the second layer of electrically conductive traces;

after forming the third layer of electrically conductive traces, removing regions of the metallic powder that do not form the electrically conductive traces; and

depositing an insulating material onto the carrier, wherein the insulating material provides an insulating substrate that supports the traces.

9. The circuit interconnecting substrate of claim 8 , further including a semiconductor die mounted thereon and wherein bonding pads on an active surface of the die are electrically coupled to the traces.

10. The circuit interconnecting substrate of claim 8 , wherein the structure is a circuit board.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0438. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0136 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0498 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0479 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0438 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0763 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0522 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 032845/0497 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2014
From: FOONG, CHEE SENG; TAN, LAN CHU
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031934/0345 →
Continuity (1)
Related Publication 20150201489A1 · Jul 16, 2015