Bit-level register file updates in extensible processor architecture
This document discusses, among other things, systems and methods to receive an instruction to selectively update a value of one or more selected bits of a first register, to receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged, and to selectively update the value of the one or more selected bits of the first register using a first write port without receiving the value of the one or more selected bits of the first register. In an example, the value of the one or more selected bits of the first register can be updated without receiving the value of the first register, in certain applications, reducing the number of read ports required to update the value of the first register.
1. A method, comprising:
receiving an instruction to selectively update a value of one or more selected bits of a first register without requiring a value of the first register file to be read;
receiving the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged; and
selectively updating the value of the one or more selected bits of the first register, using a first write port, without receiving the value of the one or more selected bits of the first register to remain unchanged.
2. The method of claim 1 , wherein the first register includes a first set of bits and the one or more selected bits define a proper subset of the first set of bits.
3. The method of claim 1 , wherein the instruction to selectively update the value of the one or more selected bits of the first register includes a bit level kill signal defining the one or more selected bits of the first register to be updated.
4. The method of claim 1 , wherein the selectively updating the value includes leaving the remaining bits of the first register unchanged.
5. The method of claim 1 , including:
receiving a value of one or more selected bits of a second register using a first read port; and
determining an updated value of the one or more selected bits of the first register using the value of the one or more selected bits of the second register.
6. The method of claim 1 , including:
receiving a value of one or more selected bits of a second register using a first read port,
wherein the selectively updating the value of the one or more selected bits of the first register includes selectively updating the value of the one or more selected bits of the first register with the value of one or more selected bits of the second register using a set of read/write ports consisting of the first read port and the first write port.
7. The method of claim 1 , including:
receiving a kill signal,
wherein the selectively updating the value to the one or more selected bits of the first register includes:
writing the updated value to the one or more selected bits of the first register when the kill signal includes a first value; and
not writing the updated value to the one or more selected bits of the first register when the kill signal includes a second value.
8. The method of claim 7 , wherein the receiving the kill signal includes reading the value of a third register using a second read port,
wherein the writing the updated value to the one or more selected bits of the first register includes when the value of a specified bit of the third register is zero, and
wherein the not writing the value to the one or more selected bits of the first register includes when the value of the specified bit of the third register is one.
9. A system, comprising:
a register file including a first register;
a set of read/write ports configured to selectively update the value of the first register; and
a processor configured to:
receive an instruction to selectively update a value of one or more selected bits of the first register;
receive the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged; and
selectively update the value of the one or more selected bits of the first register using a first write port in response to the received instruction without receiving the value of the one or more selected bits of the first register to remain unchanged and without requiring a value of the first register file to be read.
10. The system of claim 9 , wherein the first register includes a first set of bits and the one or more selected bits define a proper subset of the first set of bits.
11. The system of claim 9 , wherein the instruction to selectively update the value of the one or more selected bits of the first register includes a bit level kill signal defining the one or more selected bits of the first register to be updated.
12. The system of claim 9 , wherein the processor is configured to selectively update the value of the one or more selected bits of the first register and leave the remaining bits of the first register unchanged.
13. The system of claim 9 , wherein the processor is configured to:
receive a value of one or more selected bits of a second register using a first read port; and
determine the updated value of the one or more selected bits of the first register using the value of the one or more selected bits of the second register.
14. The system of claim 9 , wherein the set of read/write ports consists of the first write port and a first read port,
wherein the processor is configured to:
receive a value of one or more selected bits of a second register using the first read port; and
selectively update the value of the one or more selected bits of the first register with the value of one or more selected bits of the second register using a set of read/write ports.
15. The system of claim 9 , wherein the processor is configured to:
receive a kill signal;
write the updated value to the one or more selected bits of the first register when the kill signal includes a first value; and
not write the updated value to the one or more selected bits of the first register when the kill signal includes a second value.
16. The system of claim 15 , wherein the processor is configured to:
read the value of a third register using a second read port to receive the kill signal;
write the updated value to the one or more selected bits of the first register when the value of a specified bit of the third register is zero; and
not write the value to the one or more selected bits of the first register includes when the value of the specified bit of the third register is one.
17. A non-transitory machine readable medium including instructions that, when executed by a machine, cause the machine to perform operations including:
receiving an instruction to selectively update a value of one or more selected bits of a first register;
receiving the one or more selected bits of the first register to be updated and one or more selected bits of the first register to remain unchanged; and
selectively updating the value of the one or more selected bits of the first register, using a first write port, without receiving the value of the one or more selected bits of the first register to remain unchanged and without requiring a value of the first register file to be read.
18. The non-transitory machine readable medium of claim 17 , wherein the first register includes a first set of bits and the one or more selected bits define a proper subset of the first set of bits.
19. The non-transitory machine readable medium of claim 17 , wherein the instruction to selectively update the value of the one or more selected bits of the first register includes a bit level kill signal defining the one or more selected bits of the first register to be updated.
20. The non-transitory machine readable medium of claim 17 including instructions that, when executed by a machine, cause the machine to perform operations including:
receiving a value of one or more selected bits of a second register using a first read port,
wherein the selectively updating the value of the one or more selected bits of the first register includes selectively updating the value of the one or more selected bits of the first register with the value of one or more selected bits of the second register using a set of read/write ports consisting of the first read port and the first write port.