Multi level indirect predictor using confidence counter and program counter address filter scheme

1. A method for predicting simple and polymorphic branch instructions, comprising:

detecting that a program instruction is an indirect branch instruction;

determining whether a program counter for the indirect branch instruction is stored in a program counter filter;

based on the program counter not being stored in the program counter filter and being stored in a first level predictor, retrieving a predicted target for the indirect branch instruction from the first level predictor; and

based on the program counter being stored in the program counter filter, accessing a second level predictor with the program counter and a global history for the indirect branch instruction as a tag to determine whether there is a predicted target for the indirect branch instruction, and setting a program counter filter hit bit in the indirect branch instruction, wherein the indirect branch instruction carries the program counter filter hit bit down an instruction pipeline to indicate that the indirect branch instruction should not be allocated in the first level predictor when the indirect branch instruction is retired.

2. The method of claim 1 , further comprising:

retiring the indirect branch instruction and, based on the program counter combined with a global branch history not being stored in the second level predictor, storing the program counter combined with the global branch history and a target of the indirect branch instruction in the second level predictor.

3. The method of claim 1 , wherein the second level predictor is used to predict the polymorphic branch instructions.

4. The method of claim 1 , further comprising:

retiring the indirect branch instruction; and

allocating the indirect branch instruction in the first level predictor based on the program counter not being stored in the first level predictor and the program counter filter hit bit for the indirect branch instruction not being set.

5. The method of claim 4 , storing the program counter combined with a global branch history and a target of the indirect branch instruction in the second level predictor based on the program counter not being stored in the first level predictor and the program counter filter hit bit for the indirect branch instruction being set.

6. The method of claim 1 , further comprising:

based on the predicted target of the indirect branch instruction being a correct target, incrementing a confidence counter associated with the indirect branch instruction upon retirement of the indirect branch instruction; and

based on the predicted target of the indirect branch instruction not being the correct target, decrementing a confidence counter associated with the indirect branch instruction upon retirement of the indirect branch instruction.

7. The method of claim 6 , further comprising:

based on the confidence counter being less than or equal to a threshold, removing the program counter from the first level predictor and storing the program counter in the program counter filter.

8. The method of claim 1 , wherein the first level predictor is used to predict simple branch instructions.

9. An apparatus for predicting simple and polymorphic branch instructions, comprising:

logic configured to detect that a program instruction is an indirect branch instruction;

logic configured to determine whether a program counter for the indirect branch instruction is stored in a program counter filter;

logic configured to retrieve a predicted target for the indirect branch instruction from a first level predictor based on the program counter not being stored in the program counter filter and being stored in the first level predictor; and

logic configured to access a second level predictor with the program counter and a global history for the indirect branch instruction as a tag to determine whether there is a predicted target for the indirect branch instruction, and to set a program counter filter hit bit in the indirect branch instruction, wherein the indirect branch instruction carries the program counter filter hit bit down an instruction pipeline to indicate that the indirect branch instruction should not be allocated in the first level predictor when the indirect branch instruction is retired, based on the program counter being stored in the program counter filter.

10. The apparatus of claim 9 , further comprising:

logic configured to store, upon retirement of the indirect branch instruction and based on the program counter combined with a global branch history not being stored in the second level predictor, the program counter combined with the global branch history and a target of the indirect branch instruction in the second level predictor.

11. The apparatus of claim 9 , wherein the second level predictor is used to predict polymorphic branch instructions.

12. The apparatus of claim 9 , further comprising:

logic configured to allocate the indirect branch instruction to the first level predictor based on the program counter not being stored in the first level predictor and the program counter filter hit bit for the indirect branch instruction not being set upon retirement of the indirect branch instruction.

13. The apparatus of claim 12 , further comprising:

logic configured to store, based on the program counter not being stored in the first level predictor and the program counter filter hit bit for the indirect branch instruction not being set, the program counter combined with a global branch history and a target of the indirect branch instruction in the second level predictor.

14. The apparatus of claim 9 , further comprising:

logic configured to increment a confidence counter associated with the indirect branch instruction upon retirement of the indirect branch instruction based on the predicted target of the indirect branch instruction being a correct target; and

logic configured to decrement the confidence counter associated with the indirect branch instruction upon retirement of the indirect branch instruction based on the predicted target of the indirect branch instruction not being the correct target.

15. The apparatus of claim 14 , further comprising:

logic configured to remove, based on the confidence counter being less than or equal to a threshold, the program counter from the first level predictor and sto store the program counter in the program counter filter.

16. The apparatus of claim 9 , wherein the first level predictor is used to predict simple branch instructions.

17. An apparatus for predicting simple and polymorphic branch instructions, comprising:

means for detecting that a program instruction is an indirect branch instruction;

means for determining whether a program counter for the indirect branch instruction is stored in a program counter filter;

means for retrieving a predicted target for the indirect branch instruction from a first level predictor based on the program counter not being stored in the program counter filter and being stored in a first level predictor; and

means for accessing a second level predictor with the program counter and a global history for the indirect branch instruction as a tag to determine whether there is a predicted target for the indirect branch instruction, and setting a program counter filter hit bit in the indirect branch instruction, wherein the indirect branch instruction carries the program counter filter hit bit down an instruction pipeline to indicate that the indirect branch instruction should not be allocated in the first level predictor when the indirect branch instruction is retired, based on the program counter being stored in the program counter filter.