IP Library Granted Patent US 9,478,571
Granted Patent B1
US 9,478,571 · App. 14/286,063 · Granted Oct 25, 2016

Buried channel deeply depleted channel transistor

Inventors: Teymur Bakhishev (San Jose, CA); Lingquan Wang (Irvine, CA); Dalong Zhao (San Jose, CA); Pushkar Ranade (Los Gatos, CA); Scott E. Thompson (Gainesville, FL)
Assignee: Mie Fujitsu Semiconductor Limited
H01L27/14616H01L29/66477H01L29/7838
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Quick Facts
Patent No.
US 9,478,571
App. No.
14/286,063
Granted
Oct 25, 2016
Kind
B1
Abstract

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Claims (18)

1. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having one or more first device regions of a first conductivity type;

adding at least one first dopant of the first conductivity type into at least one of the first device regions to define a screening layer of the first conductivity type at the surface of the semiconductor substrate and having an effective doping density that is substantially higher than an effective doping density of the first device regions;

forming a substantially undoped layer of semiconducting material at least over the at least one of the first device regions;

adding at least one second dopant of a second conductivity type into the substantially undoped layer over the at least one of the first device regions to define a channel layer above the screening layer; and

forming gate structures and associated source and drain regions of the second conductivity type separated by a channel length in the first device regions to define MOSFET devices.

2. The method of claim 1 , wherein the forming comprises depositing a blanket epitaxial layer of the semiconductor material over the surface of the semiconductor substrate.

3. The method of claim 1 , wherein the adding of the at least one first dopant comprises implanting the at least one first dopant using implant conditions that result in an effective doping density of the first conductivity type in the screening region that is between about 10 18 cm −3 to 5×10 20 cm −3 .

4. The method of claim 1 , wherein the adding of the at least one second dopant comprises implanting the at least one second dopant using implant conditions that result in an effective doping density of the second conductivity type in the channel layer to be much less than an effective doping density of the source region and the drain region, by up to a few orders of magnitude or more.

5. The method of claim 1 , wherein the forming of the source and drain regions comprises implanting one or more dopants of the second conductivity type in the at least one of the first device regions using implant conditions that result in the screening layer being located below and between the source and drain regions.

6. A method of fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate having one or more first device regions of a first conductivity type;

adding at least one first dopant of the first conductivity type into at least one of the first device regions to define a screening layer of the first conductivity type below the surface of the semiconductor substrate and a substantially undoped channel layer above the screening layer, the screening layer having an effective doping density that is substantially higher than an effective doping density of the first device regions;

adding at least one second dopant of a second conductivity type into the substantially undoped channel layer; and

forming gate structures and associated source and drain regions of the second conductivity type separated by a channel length in the first device regions to define MOSFET devices.

7. The method of claim 6 , wherein the adding of the at least one first dopant comprises implanting the at least one first dopant using implant conditions that result in an effective doping density of the first conductivity type in the screening layer that is between about 10 18 cm −3 to 5×10 20 cm −3 .

8. The method of claim 6 , wherein the adding of the at least one second dopant comprises implanting the at least one second dopant using implant conditions that result in an effective doping density of the second conductivity type in the channel layer to be much less than an effective doping density of the source region and the drain region, by up to a few orders of magnitude or more.

9. The method of claim 6 , wherein the forming of the source and drain regions comprises implanting one or more dopants of the second conductivity type in the at least one of the first device regions using implant conditions that result in the screening layer being located below and between the source and drain regions.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: SU VOLTA, INC.
To: MIE FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 035508/0113 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2014
From: BAKHISHEV, TEYMUR; WANG, LINGQUAN; ZHAO, DALONG; RANADE, PUSHKAR; THOMPSON, SCOTT E.
To: SUVOLTA, INC.
Reel/Frame 033091/0074 →
Continuity (1)
Provisional Application 61827070 · May 24, 2013