IP Library › Granted Patent US 9,479,143
Granted Patent B2
US 9,479,143 · App. 14/670,536 · Granted Oct 25, 2016

Semiconductor device

Inventor: Jun Koyama (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H03K3/012G11C5/147G11C8/04H01L21/8258H01L27/0629H01L27/088H01L27/1225H01L29/045H01L29/7869H01L29/78693H03K3/0372H03K3/0375H03K19/0008H01L21/823412
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Quick Facts
Patent No.
US 9,479,143
App. No.
14/670,536
Granted
Oct 25, 2016
Kind
B2
Abstract

Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

Claims (46)

1. A semiconductor device comprising:

a sequential circuit comprising:

a first transistor comprising a first terminal, a second terminal, and a gate; and

a capacitor,

wherein the first transistor comprises a semiconductor layer comprising a channel formation region,

wherein the semiconductor layer comprises indium, zinc, and oxygen, and

wherein a node electrically connected to one electrode of the capacitor and the first terminal of the first transistor is configured to be in a floating state when the first transistor is in an off state.

2. The semiconductor device according to claim 1 , wherein the semiconductor layer comprises gallium.

3. The semiconductor device according to claim 2 ,

wherein the semiconductor layer comprises a crystal comprising indium, gallium, zinc, and oxygen, and

wherein a c-axis of the crystal is aligned in a direction perpendicular to a top surface of the semiconductor layer.

4. A semiconductor device comprising:

a sequential circuit comprising:

a first transistor comprising a first terminal, a second terminal, and a gate;

a logic gate; and

a capacitor,

wherein the first transistor comprises a first semiconductor layer comprising a channel formation region,

wherein the first semiconductor layer comprises indium, zinc, and oxygen,

wherein an input terminal of the logic gate is electrically connected to the first terminal of the first transistor, and

wherein a node electrically connected to one electrode of the capacitor and the first terminal of the first transistor is configured to be in a floating state when the first transistor is in an off state.

5. The semiconductor device according to claim 4 , wherein the first semiconductor layer comprises gallium.

6. The semiconductor device according to claim 5 ,

wherein the first semiconductor layer comprises a crystal comprising indium, gallium, zinc, and oxygen, and

wherein a c-axis of the crystal is aligned in a direction perpendicular to a top surface of the first semiconductor layer.

7. A semiconductor device comprising:

a register comprising:

a sequential circuit comprising:

a first transistor comprising a first terminal, a second terminal, and a gate; and

a capacitor;

a power-gating control circuit; and

a second transistor electrically connected to the sequential circuit and the power-gating control circuit so as to control supply of power supply potential to the sequential circuit in accordance with a signal output from the power-gating control circuit,

wherein the first transistor comprises a first semiconductor layer comprising a channel formation region,

wherein the first semiconductor layer comprises indium, zinc, and oxygen, and

wherein a node electrically connected to one electrode of the capacitor and the first terminal of the first transistor is configured to be in a floating state when the first transistor is in an off state.

8. The semiconductor device according to claim 7 , comprising a register controller comprising the power-gating control circuit, wherein a gate of the second transistor is electrically connected to the power-gating control circuit.

9. The semiconductor device according to claim 7 , wherein the first semiconductor layer comprises gallium.

10. The semiconductor device according to claim 9 ,

wherein the first semiconductor layer comprises a crystal comprising indium, gallium, zinc, and oxygen, and

wherein a c-axis of the crystal is aligned in a direction perpendicular to a top surface of the first semiconductor layer.

11. The semiconductor device according to claim 7 ,

wherein the second transistor comprises a second semiconductor layer comprising a channel formation region, and

wherein the second semiconductor layer comprises indium, zinc, and oxygen.

12. The semiconductor device according to claim 11 , wherein the second semiconductor layer comprises gallium.

13. The semiconductor device according to claim 12 ,

wherein the second semiconductor layer comprises a crystal comprising indium, gallium, zinc, and oxygen, and

wherein a c-axis of the crystal is aligned in a direction perpendicular to a top surface of the second semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2015
From: KOYAMA, JUN
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 035552/0572 →
Priority Claims (2)
JP 2010-178167 · Aug 6, 2010 · national
JP 2011-108342 · May 13, 2011 · national
Continuity (3)
Continuation 14037450 · Sep 26, 2013
Continuation 13196250 · Aug 2, 2011
Related Publication 20150280691A1 · Oct 1, 2015