High performance interconnect link layer
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
1. An apparatus comprising:
I/O logic to:
identify transaction data;
generate a flit from the transaction data, wherein the flit is to include two or more slots, a payload, a floating payload field to extend one of the two or more slots, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload; and
send the flit to the device over a serial data link.
2. The apparatus of claim 1 , wherein the I/O logic comprises a layered stack comprising physical layer logic, link layer logic, and protocol layer logic.
3. The apparatus of claim 1 , wherein the two or more slots consist of three defined slots.
4. The apparatus of claim 3 , wherein the flit comprises 192 bits.
5. The apparatus of claim 4 , wherein the first of the three slots comprises 72 bits, the second of the three slots comprises 70 bits, and third slot comprises 18 bits.
6. The apparatus of claim 5 , wherein the third slot is adapted to be encoded with one or more of acknowledgements and credit returns.
7. The apparatus of claim 5 , wherein the flit payload comprises 176 bits.
8. The apparatus of claim 1 , wherein the I/O logic is further to generate the CRC value using an XOR tree.
9. The apparatus of claim 8 , wherein the XOR tree is to embody a generator polynomial.
10. The apparatus of claim 9 , wherein the polynomial comprises g(x)=(x 16 +x 15 +x 13 +x 12 +x 10 +x 9 +x 8 +x 7 +x 6 +x 4 +x 3 +x 1 +1).
11. The apparatus of claim 1 , wherein the I/O logic is further to generate a rolling CRC value.
12. The apparatus of claim 11 , wherein the data link comprises at least 8 lanes in a first state and the flit comprises 192 bits.
13. The apparatus of claim 12 , wherein the first state comprises a partial width transmitting state and a full width transmitting state comprises a 20 lane link.
14. An apparatus comprising:
I/O logic to:
receive a flit, wherein the flit is to include two or more slots, a payload, a floating payload field to extend one of the two or more slots, and a cyclic redundancy check (CRC) field encoded with a 16-bit CRC value generated based on the payload; and
determine a comparison CRC value from the payload; and
compare the comparison CRC value to the CRC value included in the flit.
15. The apparatus of claim 14 , wherein the I/O logic is further to detect one or more errors on the data link based on the comparison.
16. The apparatus of claim 14 , wherein the flit comprises 192 bits, a first of the slots comprises 72 bits, a second of the slots comprises 70 bits, and a third of the slots comprises 18 bits.
17. The apparatus of claim 14 , wherein the I/O logic is further to derive the CRC value using an XOR tree.
18. The apparatus of claim 17 , wherein the XOR tree is to embody a generator polynomial.
19. The apparatus of claim 18 , wherein the generator polynomial comprises g(x)=(x 16 +x 15 +x 13 +x 12 +x 10 +x 9 +x 8 +x 7 +x 6 +x 4 +x 3 +x 1 +1).
20. The apparatus of claim 18 , wherein the generator polynomial is the same used to generate the CRC value included in the flit.
21. The apparatus of claim 14 , wherein the CRC value comprises a rolling CRC value.
22. A method comprising:
receiving a flit over a serial data link, wherein the flit has a defined format, the format defines two or more slots to be included in the flit and a floating payload field to optionally extend one of the two or more slots, and the flit includes a payload and a cyclic redundancy check (CRC) field encoded with a 16-bit CRC value generated based on the payload; and
processing the flit to derive a comparison CRC value from the payload; and
comparing the comparison CRC value to the CRC value included in the flit.
23. The method of claim 22 , wherein the flit comprises 192 bits, a first of the slots comprises 72 bits, a second of the slots comprises 70 bits, and a third of the slots comprises 18 bits.
24. The method of claim 23 , wherein the payload comprises 176 bits.
25. The method of claim 24 , further comprising detecting an error based on the comparing.
26. The method of claim 22 , further comprising identifying that the CRC value is a rolling CRC value, wherein the CRC value is processed as a rolling CRC value.
27. A system comprising:
a first device; and
a second device communicatively coupled to the first device using a serial data link, the second device including a link layer module executed by at least one processor to:
identify transaction data to be sent to the first device on the data link;
generate a flit having a defined format, wherein the format defines two or more slots to be included in the flit and a floating payload field to optionally extend one of the two or more slots, and the flit includes a payload and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload; and
send the flit to the first device over the data link.
28. The system of claim 27 , wherein the first device comprises a microprocessor.
29. The system of claim 28 , wherein the second device comprises at least one of a second microprocessor and a graphics accelerator.
30. The system of claim 27 , wherein the first device includes link layer logic to:
receive the flit; and
derive a comparison CRC value from the payload; and
compare the comparison CRC value to the CRC value included in the flit to detect an error on the data link.