Pulling devices for driving data lines

1. A circuit, comprising:

a first data line;

a second data line;

a first pulling device coupled to the first data line and a first voltage, the first pulling device being configured to:

be activated or deactivated responsive to a first control signal; and

pull a first signal at the first data line toward a voltage level of the first voltage based on a second signal at the second data line when the first pulling device is activated;

a second pulling device coupled to the second data line and the first voltage, the second pulling device being configured to:

be activated or deactivated responsive to a second control signal; and

pull a second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated;

a third pulling device coupled to the first data line and a second voltage, the third pulling device being configured to pull the first signal at the first data line toward a voltage level of the second voltage based on the first control signal; and

a fourth pulling device coupled to the second data line and the second voltage, the fourth pulling device being configured to pull the second signal at the second data line toward the voltage level of the second voltage based on the second control signal.

2. The circuit of claim 1 , further comprising:

a control circuit configured to

generate the first control signal based on at least a write control signal and a first write data signal; and

generate the second control signal based on at least the write control signal and a second write data signal.

3. The circuit of claim 2 , wherein

the control circuit is configured to generate the first control signal and the second control signal such that a first voltage swing of the first control signal or the second control signal differs from a second voltage swing from the voltage level of the first voltage to the voltage level of the second voltage.

4. The circuit of claim 2 , wherein

the control circuit is further configured to:

generate the first control signal based on a column selection signal; and

generate the second control signal based on the column selection signal.

5. The circuit of claim 2 , wherein

the control circuit comprises two NOR gates; or

the control circuit comprises two NAND gates.

6. The circuit of claim 1 , further comprising:

a precharge circuit configured to charge the first data line and the second data line to a predetermined voltage level.

7. The circuit of claim 6 , wherein the precharge circuit is configured to receive the first voltage and to use the voltage level of the first voltage as the predetermined voltage level.

8. The circuit of claim 1 , wherein

the voltage level of the first voltage is greater than the voltage level of the second voltage;

the first pulling device comprises a first P-type transistor;

the second pulling device comprises a second P-type transistor;

the third pulling device comprises a first N-type transistor; and

the fourth pulling device comprises a second N-type transistor.

9. The circuit of claim 1 , wherein

the voltage level of the first voltage is less than the voltage level of the second voltage;

the first pulling device comprises a first N-type transistor;

the second pulling device comprises a second N-type transistor;

the third pulling device comprises a first P-type transistor; and

the fourth pulling device comprises a second P-type transistor.

10. A circuit, comprising:

a first data line;

a second data line;

a first voltage node configured to carry a first voltage;

a second voltage node configured to carry a second voltage;

a control circuit;

a first transistor and a second transistor coupled in series between the first voltage node and the first data line;

a third transistor and a fourth transistor coupled in series between the first voltage node and the second data line;

a fifth transistor coupled between the second voltage node and the first data line, a gate of the fifth transistor being coupled with the control circuit; and

a sixth transistor coupled between the second voltage node and the second data line, a gate of the sixth transistor being coupled with the control circuit.

11. The circuit of claim 10 , wherein

the first transistor and the third transistor are transistors of a first type; and

the fifth transistor and the sixth transistor are transistors of a second type different from the first type.

12. The circuit of claim 11 , wherein

the second transistor and the fourth transistor are transistors of the first type.

13. The circuit of claim 11 , wherein the circuit has one of the following conditions:

the first transistor and the third transistor are P-type transistors and the fifth transistor and the sixth transistor are N-type transistors; or

the first transistor and the third transistor are N-type transistors and the fifth transistor and the sixth transistor are P-type transistors.

14. The circuit of claim 10 , wherein the circuit has one set of the following sets of conditions:

a first set of conditions including:

a source of the first transistor is coupled with the first voltage node;

a drain of the first transistor is coupled with the second transistor;

a source of the third transistor is coupled with the first voltage node; and

a drain of the third transistor is coupled with the fourth transistor; or

a second set of conditions including:

a source of the first transistor is coupled with the second transistor;

a drain of the first transistor is coupled with the first data line;

a source of the third transistor is coupled with the fourth transistor; and

a drain of the third transistor is coupled with the second data line.

15. The circuit of claim 10 , wherein the control circuit comprises:

a first logic gate having an output coupled with the gate of the second transistor and the gate of the fifth transistor, the first logic gate being configured to receive a write control signal and a first write data signal;

a second logic gate having an output coupled with the gate of the second transistor and the gate of the fifth transistor, the second logic gate being configured to receive the write control signal and a second write data signal; and

the first logic gate and the second logic gate are both NOR gates or both NAND gates.

16. The circuit of claim 15 , wherein

the control circuit is configured to generate the first control signal at the output of the first logic gate and a second control signal at the output of the second logic gate; and

the control circuit is configured such that a first voltage swing of the first control signal or the second control signal differs from a second voltage swing from a voltage level of the first voltage to a voltage level of the second voltage.

17. The circuit of claim 10 , further comprising:

a precharge circuit configured to charge the first data line and the second data line to a voltage level of the first voltage.

18. A method of driving a first data line and a second data line, the method comprising:

charging the first data line and the second data line to a predetermined voltage level;

responsive to a first write data signal, a second write data signal, and one or more of a write control signal or a column selection signal,

activating a pulling device of a first pulling device or a second pulling device and deactivating the other pulling device of the first pulling device or the second pulling device, the first pulling device being between the first data line and a first voltage node configured to carry a first voltage, and the second pulling device being between the second data line and the first voltage node;

pulling a signal at a data line of the first data line or the second data line that corresponds to the activated pulling device to a voltage level of the first voltage; and

pulling a signal at the other data line of the first data line or the second data line that corresponds to the deactivated pulling device to a voltage level of a second voltage.

19. The method of claim 18 , further comprising:

responsive to a reset signal, activating the first pulling device and the second pulling device.

20. The method of claim 18 , wherein

a third pulling device is coupled with the first data line and a second voltage node configured to carry the second voltage;

a fourth pulling device is coupled with the second data line and the second voltage node; and

pulling the signal at the other data line that corresponds to the deactivated pulling device comprises activating a pulling device of the third pulling device or the fourth pulling device that corresponds to the other data line.