Crystalline multiple-nanosheet III-V channel FETs

1. A field effect transistor, comprising:

a body layer comprising a crystalline semiconductor channel region therein; and

a gate stack on the channel region, the gate stack comprising a crystalline semiconductor gate layer and a crystalline semiconductor gate dielectric layer between the crystalline semiconductor gate layer and the crystalline semiconductor channel region,

wherein respective crystal structures of the crystalline semiconductor gate dielectric layer and the crystalline semiconductor channel region are lattice-matched, and wherein the crystalline semiconductor gate dielectric layer is not configured to supply free charge carriers to the crystalline semiconductor channel region.

2. The transistor of claim 1 , wherein the gate dielectric layer comprises a high-k crystalline semiconductor layer directly on the channel region.

3. The transistor of claim 2 , wherein the channel region, the gate dielectric layer, and the gate layer comprise respective heteroepitaxial semiconductor layers.

4. The transistor of claim 2 , wherein the channel region has a thickness of less than about 10 nanometers, and wherein the channel region is separated from the gate layer by less than about 3 nanometers.

5. The transistor of claim 4 , wherein the gate layer comprises respective crystalline semiconductor gate layers on opposing surfaces of the channel region, and wherein the gate dielectric layer comprises respective gate dielectric layers between the respective gate layers and the opposing surfaces of the channel region.

6. The transistor of claim 5 , wherein the respective gate layers on the opposing surfaces of the channel region comprise primary gate layers, and further comprising:

a secondary gate layer on sidewalls of the channel region between the opposing surfaces thereof,

wherein the secondary gate layer comprises a metal or doped polycrystalline material.

7. The transistor of claim 6 , wherein a structure comprising the gate stack and the body layer is repeatedly stacked to define a plurality of individually-gated channel regions.

8. The transistor of claim 7 , wherein the plurality of individually-gated channel regions define a fin protruding from a substrate, and wherein the secondary gate layer extends on opposing sidewalls of the fin and on a surface therebetween.

9. The transistor of claim 6 , further comprising:

amorphous insulating layers separating the sidewalls of the channel region from the secondary gate layer.

10. The transistor of claim 1 , further comprising:

source/drain regions on opposite ends of the channel region and adjacent the gate stack thereon; and

amorphous insulating layers in recessed regions of opposing sidewalls of the gate layer and separating the opposing sidewalls of the gate layer from the source/drain regions.

11. The transistor of claim 1 , wherein an interface between the channel region and the gate stack is free of low-k crystalline buffer layers.

12. The transistor of claim 1 , wherein an interface between the channel region and the gate stack is free of amorphous materials.

13. The transistor of claim 1 , wherein the channel region, the gate dielectric layer, and/or the gate layer comprise III-V or II-VI semiconductor materials.

14. The transistor of claim 13 , wherein the gate dielectric layer comprises a wide bandgap II-VI semiconductor material, and wherein the gate layer comprises a moderate bandgap III-V semiconductor material.

15. The transistor of claim 13 , wherein the channel region comprises indium arsenide (InAs), the gate dielectric layer comprises zinc telluride (ZnTe), and the gate layer comprises aluminum antimonide (AlSb).

16. The transistor of claim 13 , wherein the gate layer comprises gallium antimonide (GaSb), the gate dielectric layer comprises zinc telluride (ZnTe), and the channel region comprises indium antimonide (InSb).

17. A field effect transistor, comprising:

a nanosheet stack comprising a plurality of individually gated conduction channels, the individually gated conduction channels respectively comprising a crystalline semiconductor channel region, a crystalline semiconductor gate dielectric layer on the crystalline semiconductor channel region, and a crystalline semiconductor gate layer on the crystalline semiconductor gate dielectric layer opposite the crystalline semiconductor channel region,

wherein a portion of the crystalline semiconductor gate dielectric layer that extends from a source region to a drain region on opposite sides of the crystalline semiconductor channel region is not configured to supply free charge carriers to the crystalline semiconductor channel region, and

wherein the crystalline semiconductor channel region, the crystalline semiconductor gate dielectric layer, and the crystalline semiconductor gate layer comprise lattice-matched heteroepitaxial layers.