System and method for managing bandwidth and power consumption through data filtering
Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.
1. A method for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”), the method comprising:
monitoring transactions of one or more master components, wherein the transactions are associated with a closely coupled memory component;
filtering the transactions to identify transactions with ephemeral data content, wherein filtering the transactions to identify transactions with ephemeral data content comprises filtering transactions upstream of the closely coupled memory component; and
for one or more transactions identified to have ephemeral data content, blocking ephemeral data content from being written back from the closely coupled memory component to a long term memory component;
wherein blocking ephemeral data content from being written back from the closely coupled memory component to the long term memory component optimizes bandwidth utilization of a bus.
2. The method of claim 1 , further comprising filtering transactions downstream of the closely coupled memory component.
3. The method of claim 2 , wherein filtering the transactions downstream of the closely coupled memory component comprises filtering a transaction based on a memory address in the long term memory component associated with the filtered transaction.
4. The method of claim 2 , wherein blocking ephemeral data content from being written back from the closely coupled memory component to a long term memory component comprises dropping the one or more identified transaction upon its eviction from the closely coupled memory component.
5. The method of claim 1 , wherein filtering the transactions to identify transactions with ephemeral data content comprises filtering a transaction based on identification of a master component associated with the filtered transaction.
6. The method of claim 1 , wherein filtering the transactions to identify transactions with ephemeral data content comprises filtering a transaction based on an access mode associated with the filtered transaction.
7. The method of claim 1 , wherein blocking ephemeral data content from being written back from the closely coupled memory component to a long term memory component comprises clearing a dirty bit associated with an identified transaction.
8. The method of claim 1 , wherein the long term memory component is a double data rate (“DDR”) memory component.
9. The method of claim 1 , wherein the closely coupled memory component is a low level cache (“LLC”) that comprises one of a level one (“L1”) cache, a level two (“L2”) cache, and a level three (“L3”) cache.
10. A system for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”), the system comprising:
means for monitoring transactions of one or more master components, wherein the transactions are associated with a closely coupled memory component;
means for filtering the transactions to identify transactions with ephemeral data content, wherein filtering the transactions to identify transactions with ephemeral data content comprises filtering transactions upstream of the closely coupled memory component; and
for one or more transactions identified to have ephemeral data content, means for blocking ephemeral data content from being written back from the closely coupled memory component to a long term memory component;
wherein blocking ephemeral data content from being written back from the closely coupled memory component to the long term memory component optimizes bandwidth utilization of a bus.
11. The system of claim 10 , further comprising means for filtering transactions downstream of the closely coupled memory component.
12. The system of claim 11 , wherein the means for filtering the transactions downstream of the closely coupled memory component comprises means for filtering a transaction based on a memory address in the long term memory component associated with the filtered transaction.
13. The system of claim 11 , wherein the means for blocking ephemeral data content from being written back from the closely coupled memory component to a long term memory component comprises means for dropping the one or more identified transaction upon its eviction from the closely coupled memory component.
14. The system of claim 10 , wherein the means for filtering the transactions to identify transactions with ephemeral data content comprises means for filtering a transaction based on identification of a master component associated with the filtered transaction.
15. The system of claim 10 , wherein the means for filtering the transactions to identify transactions with ephemeral data content comprises means for filtering a transaction based on an access mode associated with the filtered transaction.
16. The system of claim 10 , wherein the means for blocking ephemeral data content from being written back from the closely coupled memory component to a long term memory component comprises means for clearing a dirty bit associated with an identified transaction.
17. The system of claim 10 , wherein the long term memory component is a double data rate (“DDR”) memory component.
18. The system of claim 10 , wherein the closely coupled memory component is a low level cache (“LLC”) that comprises one of a level one (“L1”) cache, a level two (“L2”) cache, and a level three (“L3”) cache.
19. A system for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”), the system comprising:
a writeback data filter (“WDF”) module configured to:
monitor transactions of one or more master components, wherein the transactions are associated with a closely coupled memory component;
filter the transactions to identify transactions with ephemeral data content, wherein filtering the transactions to identify transactions with ephemeral data content comprises filtering transactions upstream of the closely coupled memory component; and
for one or more transactions identified to have ephemeral data content, block ephemeral data content from being written back from the closely coupled memory component to a long term memory component;
wherein blocking ephemeral data content from being written back from the closely coupled memory component to the long term memory component optimizes bandwidth utilization of a bus.
20. The system of claim 19 , wherein the WDF module is further configured to filter transactions downstream of the closely coupled memory component.
21. The system of claim 20 , wherein the WDF module is further configured to filter a transaction based on a memory address associated with the filtered transaction.
22. The system of claim 20 , wherein the WDF module is further configured to drop the one or more identified transaction upon its eviction from the closely coupled memory component.
23. The system of claim 19 , wherein the WDF module is further configured to filter a transaction based on identification of a master component associated with the filtered transaction.
24. The system of claim 19 , wherein the WDF module is further configured to filter a transaction based on an access mode associated with the filtered transaction.
25. The system of claim 19 , wherein the WDF module is further configured to clear a dirty bit associated with an identified transaction.
26. The system of claim 19 , wherein the long term memory component is a double data rate (“DDR”) memory component.
27. The system of claim 19 , wherein the closely coupled memory component is a low level cache (“LLC”) that comprises one of a level one (“L1”) cache, a level two (“L2”) cache, and a level three (“L3”) cache.