Method and apparatus for synthesis of wideband low phase noise radio frequency signals
An apparatus for synthesizing wideband radio frequency signals in the microwave region has mostly digital components. The apparatus processes and converts a signal from a stable single-frequency electrical oscillator into a lower or higher frequency electrical signal without using analog multiplier or mixer circuits. An apparatus for synthesizing a fixed phase-stable RF reference signal for use in a radar transceiver includes a phase-stable electrical oscillator which produces a single frequency sinusoidal reference signal. The apparatus converts the reference signal to an arbitrary higher or lower fixed frequency using digital logic and signal delays. The apparatus comprises low-jitter comparator, an impulse former, a gearbox retiming circuit and a recirculator circuit. An apparatus for providing wideband FM modulation of an RF signal includes circuitry for synthesizing a radio frequency signal having arbitrary tuning of center frequency and dynamic command of wideband FM and retaining low phase noise performance of the synthesized signal.
1. An apparatus for synthesizing sinusoidal radio frequency signals comprising:
an oscillator configured to output a first sinusoidal signal having a first frequency;
an impulse former configured to convert the first sinusoidal signal into a first pulse train having a first timing interval between pulses;
a gearbox configured to dilate or compress the first timing interval between pulses of the first pulse train to thereby create a second pulse train having a second timing interval between pulses and a second frequency;
a recirculator configured to delay and add pulses in the second pulse train, to the second pulse train itself, to thereby form a third pulse train comprising pulses having a third timing interval between pulses and a third frequency, the third timing interval being less than the second timing interval; and
circuitry to convert the third pulse train into an RF signal.
2. The apparatus according to claim 1 , wherein:
the gearbox is configured to skip a pulse of the first pulse train during a dilation operation.
3. The apparatus according to claim 1 , further comprising a first field-programmable gate array (FPGA) configured to:
provide first control signals to the gearbox;
provide second control signals to the recirculator; and
provide third control signals to the oscillator to control a frequency of the oscillator.
4. he apparatus according to claim 3 , wherein:
the recirculator comprises an all-digital loop configured to insert additional pulses into the second pulse train to thereby form the third pulse train.
5. The apparatus according to claim 4 , wherein:
the recirculator comprises circuitry to adjust a time delay of the second pulse train based on delay constants stored in a look-up able and indexed by addressing information output by a counter.
6. The apparatus according to claim 4 , wherein:
the recirculator further comprises a timing comparator configured to determine a timing difference between at least one pulse in the second pulse train, and at least one pulse in the third pulse train being formed, and output an error signal in response thereto, the error signal being provided to the first FPGA to adjust a delay associated with creating the third pulse train.
7. The apparatus according to claim 6 , wherein:
the error signal is used, in part, to address entries in a look-up table, said entries comprising information from which said second controls are created.
8. The apparatus according to claim 1 , further comprising a frequency adjustment circuit configured to:
compare the second frequency with a selected frequency to create a difference signal;
in response to the difference signal, adjust control data to calibrate the system to mitigate against temperature changes and/or component aging; wherein:
the control data is only adjusted during periods of non-use of the synthesized signal.
9. An apparatus for synthesizing sinusoidal radio frequency signals comprising:
an oscillator configured to output a first sinusoidal signal having a first frequency;
an impulse former configured to convert the first sinusoidal signal into a first pulse train having a first timing interval between pulses;
a gearbox configured to dilate or compress the first timing interval between pulses of the first pulse train to thereby create a second pulse train having a second timing interval between pulses and a second frequency;
a recirculator configured to delay and add pulses in the second pulse train, to the second pulse train itself, to thereby form a third pulse train comprising pulses having a third timing interval between pulses and a third frequency, the third timing interval being less than the second timing interval; and
circuitry to convert the third pulse train into an RF signal, which circuitry comprises:
a divide-by-2-circuit configured to convert the third pulse train into square wave having a second frequency higher than the first frequency;
a filter configured to remove harmonics from the square wave having the second frequency and thereby create a high frequency sinusoidal signal; and
an amplifier configured to adjust a gain of the high frequency sinusoidal signal.
10. The apparatus according to claim 9 , further comprising a first field-programmable gate array configured to:
provide first control signals to the gearbox;
provide second control signals to the recirculator;
provide third control signals to the oscillator to control a frequency of the oscillator; and
provide fourth control signals to control the filter.