IP Library › Granted Patent US 9,490,846
Granted Patent B2
US 9,490,846 · App. 14/496,356 · Granted Nov 8, 2016

Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same

Inventors: Sung-Ik Park (Daejeon, KR); Heung-Mook Kim (Daejeon, KR); Sun-Hyoung Kwon (Daejeon, KR); Nam-Ho Hur (Daejeon, KR)
Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
H03M13/1157H03M13/036H03M13/1165H04L1/0043H04L1/0057
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Quick Facts
Patent No.
US 9,490,846
App. No.
14/496,356
Granted
Nov 8, 2016
Kind
B2
Abstract

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Claims (36)

1. A low density parity check (LDPC) encoder, comprising:

first memory configured to store an LDPC codeword having a length of 16200 and a code rate of 3/15;

second memory configured to be initialized to 0; and

a processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM),

wherein the sequence is represented by the following Sequence Table:

Sequence Table

1st row:

8 372 841 4522 5253 7430 8542 9822 10550 11896 11988

2nd row:

80 255 667 1511 3549 5239 5422 5497 7157 7854 11267

3rd row:

257 406 792 2916 3072 3214 3638 4090 8175 8892 9003

4th row:

80 150 346 1883 6838 7818 9482 10366 10514 11468 12341

5th row:

32 100 978 3493 6751 7787 8496 10170 10318 10451 12561

6th row:

504 803 856 2048 6775 7631 8110 8221 8371 9443 10990

7th row:

152 283 696 1164 4514 4649 7260 7370 11925 11986 12092

8th row:

127 1034 1044 1842 3184 3397 5931 7577 11898 12339

12689

9th row:

107 513 979 3934 4374 4658 7286 7809 8830 10804 10893

10th row:

2045 2499 7197 8887 9420 9922 10132 10540 10816 11876

11st row:

2932 6241 7136 7835 8541 9403 9817 11679 12377 12810

12nd row:

2211 2288 3937 4310 5952 6597 9692 10445 11064 11272.

2. The LDPC encoder of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 3240, a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080, and a second parity part corresponding to an identity matrix included in the PCM and having a length of 11880.

3. The LDPC encoder of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part by a circulant permutation matrix (CPM) size corresponding to the PCM, and a value obtained by dividing a length of the first parity part by the CPM size.

4. The LDPC encoder of claim 3 , wherein the CPM size is 360.

5. The LDPC encoder of claim 1 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.

6. The LDPC encoder of claim 5 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by a CPM size of the PCM.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2014
From: PARK, SUNG-IK; KIM, HEUNG-MOOK; KWON, SUN-HYOUNG; HUR, NAM-HO
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 033833/0225 →
Priority Claims (2)
KR 10-2014-0106174 · Aug 14, 2014 · national
KR 10-2014-0120009 · Sep 11, 2014 · national
Continuity (1)
Related Publication 20160049954A1 · Feb 18, 2016