Two level re-order buffer
In response to detecting one or more conditions are met, a checkpoint of a current state of a thread may be created. One or more incomplete instructions may be moved from a first level of a re-order buffer to a second level of the re-order buffer. Each incomplete instruction may be currently executing or awaiting execution.
1. A method for operating a re-order buffer having a first level and a second level, the method comprising:
in response to detecting at least one condition for changing an operating mode of the re-order buffer is met, changing the operating mode of the re-order buffer from a first operating mode to a second operating mode by:
creating a checkpoint of a current state of a thread; and
moving at least one of incomplete instructions from the first level of the re-order buffer to the second level of the re-order buffer, wherein each incomplete instruction is one of currently executing and awaiting execution;
wherein the incomplete instructions in the first level of the re-order buffer are not moved to the second level of the re-order buffer in the first operating mode.
2. The method of claim 1 , further comprising:
in response to detecting a checkpoint condition, saving a second checkpoint of a second state of the thread.
3. The method of claim 1 , wherein each instruction is a micro-operation.
4. The method of claim 1 , further comprising:
in response to detecting at least one of a branch misprediction, an exception, a trap, an interrupt, and an event associated with an incomplete instruction tracked by the second level, restoring the thread to the created checkpoint.
5. The method of claim 1 , further comprising:
in response to detecting at least one stop condition for stopping the second operating mode of the re-order buffer is met, retaining incomplete instructions in the first level.
6. The method of claim 1 , wherein creating the checkpoint includes saving a current state of an instruction pointer and a current state of performance monitoring counters.
7. The method of claim 1 , wherein the at least one condition includes whether an instruction from the first level is in an incomplete state for a predetermined period of time.
8. The method of claim 1 , wherein the at least one condition includes whether the first level includes a predetermined number of instructions.
9. The method of claim 1 , wherein the second level is one of indexed directly and indexed via content addressable memory.
10. The method of claim 1 , wherein at least one entry of the re-order buffer tracks two instructions.
11. A processor comprising:
a re-order buffer including a first level and a second level;
a retirement unit;
a plurality of execution units;
wherein the processor is configured to:
in response to detecting at least one condition for changing an operating mode of the re-order buffer is met, change the operating mode of the re-order buffer from a first operating mode to a second operating mode by:
creating a checkpoint of a current state of a thread; and
moving at least one of incomplete instructions from the first level of the re-order buffer to the second level of the re-order buffer, wherein each incomplete instruction is one of currently executing and awaiting execution;
wherein the incomplete instructions in the first level of the re-order buffer are not moved to the second level of the re-order buffer in the first operating mode.
12. The processor of claim 11 , wherein the processor is further configured to:
in response to detecting a checkpoint condition, save a second checkpoint of a second state of the thread.
13. The processor of claim 11 , wherein each instruction is a micro-operation.
14. The processor of claim 11 , wherein the processor is further configured to:
in response to detecting at least one of a branch misprediction, an exception, a trap, an interrupt, and an event associated with an incomplete instruction tracked by the second level, restore the thread to the created checkpoint.
15. The processor of claim 11 , wherein the processor is further configured to:
in response to detecting at least one stop condition for stopping the second operating mode of the re-order buffer is met, retain incomplete instructions in the first level.
16. The processor of claim 11 , wherein creating the checkpoint includes saving a current state of an instruction pointer and a current state of performance monitoring counters.
17. The processor of claim 11 , wherein the at least one condition includes whether an instruction from the first level is in an incomplete state for a predetermined period of time.
18. The processor of claim 11 , wherein the at least one condition includes whether the first level includes a predetermined number of instructions.
19. The processor of claim 11 , wherein the second level is one of indexed directly and indexed via content addressable memory.
20. The processor of claim 11 , wherein at least one entry of the re-order buffer tracks two instructions.
21. A non-transitory machine-readable medium having stored thereon an instruction, which if performed by a machine causes the machine to perform a method for operating a re-order buffer having a first level and a second level, the method comprising:
in response to detecting at least one condition for changing an operating mode of the re-order buffer is met, changing the operating mode of the re-order buffer from a first operating mode to a second operating mode by:
creating a checkpoint of a current state of a thread; and
moving at least one of incomplete instructions from the first level of the re-order buffer to the second level of the re-order buffer, wherein each incomplete instruction is one of currently executing and awaiting execution;
wherein the incomplete instructions in the first level of the re-order buffer are not moved to the second level of the re-order buffer in the first operating mode.
22. The machine-readable medium of claim 21 , wherein the method further comprises:
in response to detecting a checkpoint condition, saving a second checkpoint of a second state of the thread.
23. The machine-readable medium of claim 21 , wherein each instruction is a micro-operation.
24. The machine-readable medium of claim 21 , wherein the method further comprises:
in response to detecting at least one of a branch misprediction, an exception, a trap, an interrupt, and an event associated with an incomplete instruction tracked by the second level, restoring the thread to the created checkpoint.
25. The machine-readable medium of claim 21 , wherein the method further comprises:
in response to detecting at least one stop condition for stopping the second operating mode of the re-order buffer is met, retaining incomplete instructions in the first level.
26. The machine-readable medium of claim 21 , wherein creating the checkpoint includes saving a current state of an instruction pointer and a current state of performance monitoring counters.
27. A system comprising:
a non-transitory memory to store a plurality of instructions;
a processor coupled to the memory to execute the plurality of instructions, the processor configured to operate a re-order buffer having a first level and a second level by performing:
in response to detecting at least one condition for changing an operating mode of the re-order buffer is met, change the operating mode of the re-order buffer from a first operating mode to a second operating mode by:
creating a checkpoint of a current state of a thread; and
moving at least one of incomplete instructions from the first level of the re-order buffer to the second level of the re-order buffer, wherein each incomplete instruction is one of currently executing and awaiting execution;
wherein the incomplete instructions in the first level of the re-order buffer are not moved to the second level of the re-order buffer in the first operating mode.
28. The system of claim 27 , wherein the processor is further configured to:
in response to detecting a checkpoint condition, save a second checkpoint of a second state of the thread.
29. The system of claim 27 , wherein each instruction is a micro-operation.
30. The system of claim 27 , wherein the processor is further configured to:
in response to detecting at least one of a branch misprediction, an exception, a trap, an interrupt, and an event associated with an incomplete instruction tracked by the second level, restore the thread to the created checkpoint.