Offloading of computation for rack level servers and corresponding methods and systems

1. A method, comprising:

issuing a write command on a system memory bus by operation of a memory controller, the system memory bus including address and data lines;

receiving the write command from the system memory bus in an in-line module through an in-line module connector, an address of the write command identifying a request to at least one offload processor disposed on the in-line module;

processing at least a portion of data included with the write command with the at least one offload processor to generate processed data; and

transmitting the processed data from the in-line module over the system memory bus; wherein

the system memory bus is further connected to at least one processor connector configured to receive at least one host processor different from the at least one offload processor, that can access a system memory via the system memory bus, and

transmitting the processed data from the in-line module over the system memory bus includes transmitting the processed data to an input/output device that is different than a host processor.

2. The method of claim 1 , wherein:

receiving the write command includes processing a direct memory access (DMA) write request with an interface of the in-line module.

3. The method of claim 2 , wherein:

the DMA write request is not issued by a host processor.

4. The method of claim 2 , wherein:

the DMA write request is issued by a virtual switch different than a host processor.

5. The method of claim 1 , wherein:

receiving the write command includes storing write data corresponding to the write command in a buffer memory mounted on the in-line module.

6. The method of claim 1 , further including:

in response to predetermined conditions, storing a processing context of the at least one offload processor within the in-line module, and redirecting the at least one offload processor to process other data different from that received with the write command.

7. The method of claim 6 , further including:

after processing or terminating the processing of the other data, restoring the stored processing context to the at least one offload processor.

8. The method of claim 1 , wherein:

transmitting the processed data from the in-line module over the system memory bus includes responding to a read command on the system memory bus issued by the memory controller.

9. A method, comprising:

writing data to predetermined physical addresses of a system memory of a system, the address of the written data corresponding to at least one offload processor and identifying a request to the at least one offload processor;

configuring at least one processor module to include the predetermined physical addresses, the at least one processor module being physically connected to a system memory bus by a memory module connection, the system memory bus including address and data lines; and

processing the write data with the at least one offload processor, the at least one offload processor being mounted on the at least one processor module; wherein

the system memory includes physical addresses that include

the predetermined physical addresses, and

other physical addresses for storing data in the system memory, including by a main processor of the system, the main processor being different from the at least one offload processor and not mounted on the processor module.

10. The method of claim 9 , wherein:

writing data includes servicing a direct memory access (DMA) request at the at least one processor module.

11. The method of claim 10 , wherein:

the main processor is coupled to the system memory bus by a memory controller; and

the DMA request is initiated by device other than the main processor.

12. The method of claim 9 , further including:

the at least one processor module includes a plurality of hardware functions, including the at least one offload processor, the hardware functions being mapped to particular physical addresses of the system memory; and

scheduling operations of the hardware functions according to the write addresses received by the at least one processor module.

13. The method of claim 9 wherein:

scheduling operations of the multiple hardware functions includes

storing a current context of the at least one offload processor, and

processing other data with the at least one offload processor, the other data being different than the write data.

14. The method of claim 9 , further including:

processing the write data with the at least one offload processor generates processed data; and

outputting the processed data from the at least processor module by reading data from the predetermined physical addresses of the system memory.