IP Library › Granted Patent US 9,495,723
Granted Patent B2
US 9,495,723 · App. 14/026,410 · Granted Nov 15, 2016

Scale-up techniques for multi-GPU passthrough

Inventors: Andrew Currid (Alameda, CA); Franck Diard (Saint Contest, FR); Chenghuan Jia (Fremont, CA); Parag Kulkarni (Pune, IN)
Assignee: NVIDIA CORPORATION
G06T1/20G06F3/1438G06F9/46G09G5/363G06F9/455G06F9/5077G09G3/003G09G2360/06G09G2370/022
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Quick Facts
Patent No.
US 9,495,723
App. No.
14/026,410
Granted
Nov 15, 2016
Kind
B2
Abstract

A device for processing graphics data includes a plurality of graphics processing units. Each graphics processing unit may correspond to a virtualized operating system. Each graphics processing unit may include a configuration register indicating a 3D class code and a command register indicating that I/O cycle decoding is disabled. The device may be configured to transmit a configuration register value to a virtualized operating system indicating a VGA-compatible class code. The device may be configured to transmit a command register value to the virtualized operating system that indicates that I/O cycle decoding is enabled. In this manner, legacy bus architecture of the device may not limit the number of graphics processing units deployed in the device.

Claims (29)

1. A method for a hypervisor to virtualize register values of a graphics processing unit, the method comprising:

determining by the hypervisor that a configuration register of the graphics processing unit indicates that the device includes a 3D class code;

selecting the graphics processing unit as a primary display device for a virtualized operating system; and

virtualizing the configuration register and a command register of the graphics processing unit by transmitting a configuration register value from the hypervisor to the operating system that indicates that the graphics processing unit includes a VGA-compatible class code instead of the 3D class code included in the configuration register of the graphics processing unit and transmitting a command register value from the hypervisor to the operating system that indicates that I/O cycle decoding is enabled for the graphics processing unit.

2. The method of claim 1 , wherein the graphics processing unit is configured for communication according to a PCI bus specification.

3. The method of claim 2 , wherein the graphics processing unit is operably coupled to a PCI switch architecture that supports a limited number of devices including a VGA-compatible class code.

4. The method of claim 2 , wherein the graphics processing unit is operably coupled to a PCI switch architecture that supports a theoretical maximum of 16 graphics processing units including a VGA-compatible class code and supports more than 16 graphics processing units including a 3D class code.

5. The method of claim 1 , wherein the operating system is constrained to use a graphics processing unit including a VGA-compatible class code as a primary display device.

6. The method of claim 5 , wherein the operating system is further constrained to use a graphics processing unit indicating that I/O cycling is enabled as a primary display device.

7. The method of claim 6 , wherein the graphics processing unit is included in a server configured to support a cloud based gaming service.

8. A non-transitory computer-readable storage medium comprising instructions stored thereon, that upon execution, cause one or more processors to:

determine that a configuration register of a graphics processing unit indicates that the graphics processing unit includes a 3D class code;

select the graphics processing unit as a primary display device for a virtualized operating system; and

virtualize the configuration register and a command register of the graphics processing unit by transmitting a configuration register value to the operating system that indicates that the graphics processing unit includes a VGA-compatible class code instead of the 3D class code included in the configuration register of the graphics processing unit and transmitting a command register value to the operating system that indicates that I/O cycle decoding is enabled for the graphics processing unit device.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the a graphics processing unit is configured for communication according to a PCI bus specification.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the graphics processing unit is operably coupled to a PCI switch architecture that supports a limited number of graphics processing units including a VGA-compatible class code.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the graphics processing unit is operably coupled to a PCI switch architecture that supports a theoretical maximum of 16 graphics processing units including a VGA-compatible class code and supports more than 16 graphics processing units including a 3D class code.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the operating system is constrained to select a graphics processing unit including a VGA-compatible class code as a primary display device.

13. The non-transitory computer-readable storage medium of claim 12 , wherein the operating system is further constrained to select a graphics processing unit indicating that I/O cycling is enabled as a primary display device.

14. The non-transitory computer-readable storage medium of claim 13 , wherein the graphics processing unit is included in a server configured to support a cloud based gaming service.

15. A device for processing graphics data, the device comprising:

a plurality graphic processing units, each corresponding to one of a plurality of virtualized operating systems, wherein each of the graphics processing units includes a configuration register indicating that the graphics processing unit includes a 3D class code and a command register indicating that I/O cycle decoding is disabled for the graphics processing unit; and

a non-transitory computer readable medium having instructions stored thereon that, when executed, cause one or more processors of the device to:

virtualize the configuration register and the command register of one or more of the graphics processing units by transmitting a configuration register value to a virtualized operating system corresponding to one of the plurality of graphic processing units that indicates that the graphic processing unit includes a VGA-compatible class code instead of the 3D class indicated by the configuration register of the graphics processing unit and transmitting a command register value to the virtualized operating system corresponding to the one of the plurality of graphic processing units that indicates that I/O cycle decoding is enabled for the graphics processing unit.

16. The device of claim 15 , wherein each of the plurality of graphics processing units are operably coupled to a PCI switch architecture that supports a limited number of devices including a VGA-compatible class code configured.

17. The device of claim 15 , wherein each of the virtualized operating systems is configured to select a device including a VGA-compatible class code as a primary display device.

18. The device of claim 17 , wherein each of the virtualized operating systems is further configured to select a device indicating that I/O cycling is enabled as a primary display device.

19. The device of claim 15 , wherein the plurality of graphic processing units includes at least sixteen graphics processing units and wherein the device is a server configured to support a cloud based gaming service.

20. The device of claim 15 , wherein the plurality of graphic processing units includes three graphics processing units having a 3D controller class code and one graphics processing unit having a VGA-compatible class code.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2013
From: CURRID, ANDREW; DIARD, FRANCK; JIA, CHENGHUAN; KULKARNI, PARAG
To: NVIDIA CORPORATION
Reel/Frame 031203/0321 →
Continuity (2)
Provisional Application 61864171 · Aug 9, 2013
Related Publication 20150042664A1 · Feb 12, 2015