IP Library › Granted Patent US 9,496,039
Granted Patent B2
US 9,496,039 · App. 14/408,535 · Granted Nov 15, 2016

Storage device and method for performing interruption control thereof

Inventors: Xuebing Yin (Beijing, CN); Yilei Wang (Beijing, CN)
Assignee: MEMBLAZE TECHNOLOGY (BEIJING) CO., LTD.
G11C16/10G06F3/0611G06F3/0656G06F3/0679G06F13/28G11C2207/2245
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Quick Facts
Patent No.
US 9,496,039
App. No.
14/408,535
Granted
Nov 15, 2016
Kind
B2
Abstract

A storage device includes a flash memory and a buffer memory. A method of controlling interrupts includes: receiving data to be written to the storage device from an information processing device; writing the received data to be written to the storage device to the buffer memory; fetching the data in the buffer memory and writing the data to the flash memory; in which, after writing the received data to be written to the storage device to the buffer memory, if the amount of data in the buffer memory is less than the predetermined threshold, then sending a message indicating the completion of the write operation to the information processing device.

Claims (22)

1. A method of controlling interrupts in a storage device, wherein the storage device including a first flash memory, a second flash memory, and a buffer memory, the method comprising:

receiving data to be written to the storage device from an information processing device;

writing the received data to be written to the storage device to the buffer memory;

fetching the data in the buffer memory and writing the data to the first flash memory or the second flash memory;

sending a message to the information processing device, to indicate completion of the write request;

wherein, after writing the received data to be written to the storage device to the buffer memory,

if an amount of data in the buffer memory to be written to the first flash memory is less than a first predetermined threshold, and an amount of data in the buffer memory to be written to the second flash memory is less than a second predetermined threshold, and the number of times of sending messages, indicating completion of the write request, to the information processing device within a predetermined time interval is greater than or equal to a third predetermined threshold, then sending a message indicating completion of the write operation to the information processing device,

if the amount of data in the buffer memory to be written to the first flash memory is greater than or equal to the first predetermined threshold, or the amount of data in the buffer memory to be written to the second flash memory is greater than or equal to the second predetermined threshold, or the number of times of sending messages, indicating completion of the write request, to the information processing device within the predetermined time interval is greater than or equal to the third predetermined threshold, then catching and not sending the message indicating the completion of the write operation to the information processing device while still receiving data to be written to the storage device from the information processing device and writing data from the buffer memory into the first flash memory and the second flash memory;

wherein the first predetermined threshold and the second predetermined threshold are respectively corresponding to the amount of data that can be reliably fetched from the buffer memory and written to the first and second flash memory using a standby power.

2. The method of claim 1 , further includes, using the information processing device, accessing or setting the first predetermined threshold and the second predetermined threshold, or measuring the electrical characteristics of the standby power, and modifying the first predetermined threshold and the second predetermined threshold based on the measurement results.

3. The method of claim 1 , wherein the write request will be cached after being received from the information processing device.

4. A storage device includes a flash memory, a buffer memory, an information processing device interface and a control circuit, wherein the control circuit includes an interrupt controller, and the storage device is configured to communicably connect with an information processing device, wherein:

the information processing device interface is configured to receive a write request from the information processing device;

the control circuit, based on the write request, is configured to write data into the buffer memory;

the control circuit is configured to fetch the data in the buffer memory and to write the data to the flash memory;

the interrupt controller sends a message to the information processing device, to indicate completion of the write request;

wherein after writing the received data to be written to the storage device to the buffer memory,

if an amount of data in the buffer memory to be written to the first flash memory is less than a first predetermined threshold, and an amount of data in the buffer memory to be written to the second flash memory is less than a second predetermined threshold, and the number of times of sending messages, indicating completion of the write request, to the information processing device within a predetermined time interval is greater than or equal to a third predetermined threshold, then the interrupt controller sends a message indicating completion of the write operation to the information processing device;

if the amount of data in the buffer memory to be written to the first flash memory is greater than or equal to the first predetermined threshold, or the amount of data in the buffer memory to be written to the second flash memory is greater than or equal to the second predetermined threshold, or the number of times of sending messages, indicating completion of the write request, to the information processing device within the predetermined time interval is greater than or equal to the third predetermined threshold, then the interrupt controller caches and does not send the message indicating the completion of the write operation to the information processing device while the information processing device interface still receives data to be written to the storage device from the information processing device and writes data from the buffer memory into the first flash memory and the second flash memory;

wherein the first predetermined threshold and the second predetermined threshold are respectively corresponding to the amount of data that can be reliably fetched from the buffer memory and written to the first and second flash memory using a standby power.

5. The storage device of claim 4 , wherein the write request is cached by the control circuit after receiving the write request from the information processing device by the information processing device interface.

6. The storage device of claim 4 , wherein, the control circuit also accesses or sets the first predetermined threshold and the second predetermined threshold based on a command from the information processing device, or the control circuit measures the electrical characteristics of the standby power, and modifies the first predetermined threshold and the second predetermined threshold based on the measurement results.

Assignments (3)
CHANGE OF ADDRESS Recorded Feb 7, 2022
From: BEIJING MEMBLAZE TECHNOLOGY CO., LTD.
To: BEIJING MEMBLAZE TECHNOLOGY CO., LTD.
Reel/Frame 058963/0473 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 034670 FRAME: 0509. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 22, 2021
From: YI, XUEBING; WANG, YILEI
To: BEIJING MEMBLAZE TECHNOLOGY CO., LTD.
Reel/Frame 058896/0953 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2014
From: YIN, XUEBING; WANG, YILEI
To: MEMBLAZE TECHNOLOGY (BEIJING) CO., LTD.
Reel/Frame 034670/0509 →
Priority Claims (1)
CN 2012 1 0204083 · Jun 16, 2012 · national
Continuity (1)
Related Publication 20150155044A1 · Jun 4, 2015