Soldering three dimensional integrated circuits

1. A method comprising:

heating a three-dimensional integrated circuit to a base temperature, wherein the base temperature is below a melting temperature of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps disposed between vertically stacked dies;

activating a first on-chip heat source to reflow a first portion of the plurality of solder bumps that is within a first local-hot-zone, wherein the first local-hot-zone has a temperature that is equal to or higher than the melting temperature of the solder; and

activating a second on-chip heat source to reflow a second portion of the plurality of solder bumps that is within a second local-hot-zone, wherein the second local-hot-zone has a temperature that is equal to or higher than the melting temperature of the solder.

2. The method of claim 1 , further comprising

responsive to monitoring temperatures within the first local-hot-zone and the second local-hot-zone, using one or more thermal diodes, adjusting one or both of a heat output of the first on-chip heat source and a heat output of the second on-chip heat source.

3. The method of claim 1 , wherein the first on-chip heat source and the second on-chip heat source are each shunt resistors.

4. The method of claim 3 , wherein a heat output of one or both of the first on-chip heat source and the second on-chip heat source are increased via pulse-width modulation.

5. The method of claim 1 , wherein one or both of the first on-chip heat source and the second on-chip heat source include one or more processor cores.

6. The method of claim 5 , wherein an electrical current is supplied to both of the first on-chip heat source and the second on-chip heat source, and wherein the first on-chip heat source and the second on-chip heat source are in a quiescent state.

7. The method of claim 5 , wherein one or both of the first on-chip heat source and the second on-chip heat source are configured to execute a first scan operation.

8. The method of claim 7 , wherein a heat output of the first on-chip heat source and a heat output of the second on-chip heat source are increased by execution of a second scan operation by the first on-chip heat source and the second on-chip heat source, wherein a greater count of transistors are simultaneously active in the second scan operation when compared with a count of transistors that are simultaneously active in the first scan operation.

9. The method of claim 5 , wherein the first on-chip heat source and the second on-chip heat source are configured to execute a first computer program that provides inputs to a first plurality of logic gates and a second plurality of logic gates to generate heat, and wherein the first computer program provides inputs to the second plurality of logic gates based, at least in part, on logical outputs of the first plurality of logic gates.

10. The method of claim 9 , wherein a heat output of the first on-chip heat source and a heat output of the second on-chip heat source are increased by execution of a second computer program, wherein the second computer program provides inputs to a third plurality of logic gates and a fourth plurality of logic gates to generate heat, and wherein the second computer program provides inputs to the fourth plurality of logic gates based, at least in part, on a logical output of the third plurality of logic gates, and wherein the second computer program involves a greater average count of instructions per second when compared to an average count of instructions per second of the first computer program.

11. The method of claim 1 , further comprising:

providing heat via an external heat source to heat the three-dimensional integrated circuit to the base temperature.

12. The method of claim 11 , wherein the external heat source is a thermoelectric device.

13. The method of claim 11 , further comprising:

providing heat via a plurality of on-chip heat sources to heat the three-dimensional integrated circuit to the base temperature.

14. The method of claim 13 , wherein at least one of the plurality of on-chip heat sources includes a shunt resistor.

15. The method of claim 13 , wherein at least one of the plurality of on-chip heat sources includes a processor core.

16. The method of claim 15 , wherein at least one of the plurality of on-chip heat sources are configured to execute scan operations.

17. The method of claim 15 , wherein the plurality of on-chip heat sources are configured to execute computer programs.

18. The method of claim 13 , further comprising:

responsive to determining, using a plurality of thermal diodes, a temperature of the three-dimensional integrated circuit at a plurality of points within the three-dimensional integrated circuit, adjusting a heat output of at least one on-chip heat source.

19. The method of claim 13 , further comprising:

responsive to determining, using a plurality of thermal diodes, a temperature of the three-dimensional integrated circuit at a plurality of points within the three-dimensional integrated circuit, adjusting a heat output of the external heat source.