Receiver circuit and signal receiving method thereof
Provided is a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground.
1. A receiver circuit which receives an input signal through a pad, the receiver circuit comprising:
a first restriction circuit configured to provide a first reference voltage or an input signal to a first node, the input signal having a voltage higher than the first reference voltage;
a second restriction circuit configured to provide a second reference voltage or the input signal to a second node, the input signal having a voltage lower than the second reference voltage;
a first PMOS transistor configured to pull up an output node based on a voltage of the first node;
a first NMOS transistor configured to pull down the output node based on a voltage of the second node;
a second PMOS transistor connected between the output node and the first PMOS transistor;
a second NMOS transistor connected between the output node and the first NMOS transistor; and
at least one compensation resistor connected between a power supply voltage and one end of the first PMOS transistor or between one end of the first NMOS transistor and a ground,
wherein the first restriction circuit comprises a third PMOS transistor configured to provide the first reference voltage to the first node in response to the input signal.
2. The receiver circuit of claim 1 , wherein the first restriction circuit further comprises:
a fourth PMOS transistor configured to provide the input signal to the first node in response to the first reference voltage.
3. The receiver circuit of claim 1 , wherein the second restriction circuit comprises:
a third NMOS transistor configured to provide the second reference voltage to the second node in response to the input signal; and
a fourth NMOS transistor configured to provide the input signal to the second node in response to the second reference voltage.
4. The receiver circuit of claim 1 , wherein the first reference voltage is provided to a gate of the second PMOS transistor and the second reference voltage is provided to a gate of the second PMOS NMOS transistor.
5. The receiver circuit of claim 1 , wherein the power supply voltage is higher than at least one of the first reference voltage and the second reference voltage.
6. The receiver circuit of claim 5 , wherein the first reference voltage corresponds to a difference between the power supply voltage and the second reference voltage.
7. The receiver circuit of claim 1 , wherein the power supply voltage corresponds to the second reference voltage and the first reference voltage corresponds to a ground voltage.
8. The receiver circuit of claim 7 , wherein, when the input signal is provided by the first or second restriction circuit, the input signal is provided without modification to a level thereof.
9. The receiver circuit of claim 1 , further comprising:
a fourth PMOS transistor having a gate connected to the first node, and being connected between the first PMOS transistor and the power supply voltage; and
a third NMOS transistor having a gate connected to the second node, and being connected between the first NMOS transistor and the ground.
10. The receiver circuit of claim 9 , further comprising:
a first hysteresis setting part configured to provide a first bias voltage to a source of the first PMOS transistor based on the first reference voltage and an output signal that is output to the output node.
11. The receiver circuit of claim 10 , wherein the first hysteresis setting part comprises:
a fifth PMOS transistor configured to connect between the first reference voltage and the source of the first PMOS transistor;
a sixth PMOS transistor configured to provide the first reference voltage to a gate of the fifth PMOS transistor in response to the output signal; and
a seventh PMOS transistor configured to provide the output signal to the gate of the fifth PMOS transistor in response to the first reference signal.
12. The receiver circuit of claim 9 , further comprising:
a second hysteresis setting part configured to provide a second bias voltage to a source of the first NMOS transistor based on the second reference voltage and an output signal that is output to the output node.
13. The receiver circuit of claim 12 , wherein the second hysteresis setting part comprises:
a fourth NMOS transistor configured to connect between the second reference voltage and the source of the first NMOS transistor;
a fifth NMOS transistor configured to provide the second reference voltage to a gate of the fourth NMOS transistor in response to the output signal; and
a sixth NMOS transistor configured to provide the output signal to the gate of the fourth NMOS transistor in response to the second reference signal.
14. A receiver circuit which receives an input signal through a mad, comprising:
a first restriction circuit configured to provide the input signal higher than a first reference voltage to a first node;
a second restriction circuit configured to provide the input signal lower than a second reference voltage to a second node;
a first PMOS transistor configured to pull up an output node based on a voltage of the first node;
a first NMOS transistor configured to pull down the output node based on a voltage of the second node;
a second PMOS transistor having a gate connected to the first node, and being connected between a power supply voltage and a source of the first PMOS transistor;
a first hysteresis setting part configured to control a voltage of the source of the first PMOS transistor based on the output signal;
a second NMOS transistor having a gate connected to the second node, and being connected between a source of the first NMOS transistor and a ground; and
a second hysteresis setting part configured to control a voltage of the source of the first NMOS transistor based on the output signal.
15. The receiver circuit of claim 14 , wherein the first restriction circuit is configured to provide the first reference voltage to the first node in response to a level of the input signal being lower than the first reference voltage.
16. The receiver circuit of claim 14 , wherein the second restriction circuit is configured to provide the second reference voltage to the second node in response to a level of the input signal being higher than the second reference voltage.
17. The receiver circuit of claim 14 , further comprising:
a first compensation resistor connected between the power supply voltage and the source of the first PMOS transistor; and
a second compensation resistor connected between the ground and the source of the first NMOS transistor.
18. The receiver circuit of claim 14 , further comprising:
a third PMOS transistor connected between the output node and the first PMOS transistor; and
a third NMOS transistor connected between the output node and the first NMOS transistor.
19. The receiver circuit of claim 18 , wherein the first reference voltage is provided to a gate of the third PMOS transistor and the second reference voltage is provided to a gate of the third NMOS transistor.
20. A receiver circuit, comprising:
a first restriction circuit configured to provide an input signal higher than a first reference voltage to a first node;
a second restriction circuit configured to provide the input signal lower than a second reference voltage to a second node;
a first PMOS transistor configured to pull up an output node based on a voltage of the first node;
a first NMOS transistor configured to pull down the output node based on a voltage of the second node;
a second PMOS transistor having a gate connected to the first node, and being connected between a power supply voltage and a source of the first PMOS transistor;
a first hysteresis setting part configured to control a voltage of the source of the first PMOS transistor based on the output signal;
a second NMOS transistor having a gate connected to the second node, and being connected between a source of the first NMOS transistor and a ground; and
a second hysteresis setting part configured to control a voltage of the source of the first NMOS transistor based on the output signal,
wherein the first hysteresis setting part comprises:
a fourth PMOS transistor configured to connect between the first reference voltage and the source of the first PMOS transistor;
a fifth PMOS transistor configured to provide the first reference voltage to a gate of the fourth PMOS transistor in response to the output signal; and
a sixth PMOS transistor configured to provide the output signal to the gate of the fourth PMOS transistor in response to the first reference signal.