Hardening of direct anonymous attestation from side-channel attack

1. An apparatus comprising:

a processor circuit;

an interface operative to communicatively couple the processor circuit to a network; and

a storage communicatively coupled to the processor circuit and arranged to store instructions operative on the processor circuit to:

digitally sign a message to create a first signature using a modular arithmetic operation and a point multiplication operation, the modular arithmetic operation arranged to compensate for a value of a variable greater than a modulus without use of a branching instruction, the point multiplication operation arranged to prevent an instance of an infinite point without use of a branch instruction to compare a variable to zero, the point multiplication operation to comprise identifying a window size comprising a number of bits and an input variable comprising a first positive integer, converting the first positive integer to a second positive integer by performing operations including one or more bitwise shifts by the number of bits, and deriving a point on an elliptic curve based on the second positive integer; and

transmit the first signature to a verifying server via the network.

2. The apparatus of claim 1 , the modular arithmetic operation comprising modular negation.

3. The apparatus of claim 1 , the instructions operative on the processor circuit to perform the modular arithmetic operation by:

deriving a bitwise mask;

deriving a complement of the mask;

employing the mask in a first logical AND operation and the complement of the mask in a second logical AND operations; and

deriving a result of the modular arithmetic operation by combining the results of the first and second logical AND operations in an OR operation.

4. The apparatus of claim 1 , the instructions operative on the processor circuit to exchange signals via the network with the verifying server to select the message and a base.

5. The apparatus of claim 4 , the instructions operative on the processor circuit to exchange the base with the verifying server via the network.

6. The apparatus of claim 1 , comprising a controller, the controller comprising a random number generator, the instructions operative on the processor circuit to signal the random number generator to randomly generate a base.

7. The apparatus of claim 1 , the point multiplication operation arranged to generate a table comprising multiple entries, each entry comprising multiple bits, the bits of the multiple bits of each entry interspersed within the table to force a cache miss each time a portion of the table stored in a cache of the processor circuit is accessed.

8. The apparatus of claim 7 , the instructions operative on the processor circuit to employ elliptic curve cryptography in digitally signing the message.

9. The apparatus of claim 1 , the instructions operative on the processor circuit to:

signal an issuing server via the network to request a member private key;

create a second signature using an initial private key stored in the storage;

transmit the second signature to the issuing server; and

receive the member private key.

10. An apparatus comprising:

a processor circuit;

an interface operative to communicatively couple the processor circuit to a network; and

a storage communicatively coupled to the processor circuit and arranged to store instructions operative on the processor circuit to:

digitally sign a message to create a first signature using a point multiplication operation arranged to generate a table comprising multiple entries, each entry comprising multiple bits, the bits of the multiple bits of each entry interspersed within the table to force a cache miss each time a portion of the table stored in a cache of the processor circuit is accessed, the point multiplication operation arranged to prevent an instance of an infinite point without use of a branch instruction to compare a variable to zero, the point multiplication operation to comprise identifying a window size comprising a number of bits and an input variable comprising a first positive integer, converting the first positive integer to a second positive integer by performing operations including one or more bitwise shifts by the number of bits, and deriving a point on an elliptic curve based on the second positive integer; and

transmit the first signature to a verifying server via the network.

11. The apparatus of claim 10 , the instructions operative on the processor circuit to employ elliptic curve cryptography in digitally signing the message.

12. The apparatus of claim 10 , the instructions operative on the processor circuit to exchange signals via the network with the verifying server to select the message and a base.

13. The apparatus of claim 12 , the instructions operative on the processor circuit to exchange the base with the verifying server via the network.

14. The apparatus of claim 10 , comprising a controller, the controller comprising a random number generator, the instructions operative on the processor circuit to signal the random number generator to randomly generate a base.

15. The apparatus of claim 10 , the instructions operative on the processor circuit to digitally sign the message to create the first signature using a modular arithmetic operation arranged to compensate for a value of a variable greater than a modulus without use of a branching instruction, the modular arithmetic operation comprising one of modular addition, modular subtraction and modular negation.

16. The apparatus of claim 15 , the instructions operative on the processor circuit to perform the modular arithmetic operation by:

deriving a bitwise mask;

deriving a complement of the mask;

employing the mask in a first logical AND operation and the complement of the mask in a second logical AND operations; and

deriving a result of the modular arithmetic operation by combining the results of the first and second logical AND operations in an OR operation.

17. The apparatus of claim 10 , the instructions operative on the processor circuit to:

signal an issuing server via the network to request a member private key;

create a second signature using an initial private key stored in the storage;

transmit the second signature to the issuing server; and

receive the member private key.

18. A computer-implemented method comprising:

generating a random number;

generating a member private key from a group public key, a group private key and the random number using a point multiplication operation arranged to generate a table comprising multiple entries, each entry comprising multiple bits, the bits of the multiple bits of each entry interspersed within the table to force a cache miss each time a portion of the table stored in a cache of a processor circuit is accessed, the point multiplication operation arranged to prevent an instance of an infinite point without use of a branch instruction to compare a variable to zero, the point multiplication operation to comprise identifying a window size comprising a number of bits and an input variable comprising a first positive integer, converting the first positive integer to a second positive integer by performing operations including one or more bitwise shifts by the number of bits, and deriving a point on an elliptic curve based on the second positive integer; and

providing the member private key to a member device.

19. The computer-implemented method of claim 18 , comprising employing elliptic curve cryptography in generating the member private key.

20. The computer-implemented method of claim 18 , comprising:

receiving a signal from the member device requesting the member private key;

receiving a signature from the member device created with an initial private key; and

verifying the signature with an initial public key.

21. The computer-implemented method of claim 18 , comprising generating a group public key and a group private key using the point multiplication operation.

22. The computer-implemented method of claim 18 , generating the member private key comprises using a modular arithmetic operation arranged to compensate for a value of a variable greater than a modulus without use of a branching instruction, the modular arithmetic operation comprising one of modular addition, modular subtraction and modular negation.

23. The computer-implemented method of claim 18 , performing the modular arithmetic operation comprises:

deriving a bitwise mask;

deriving a complement of the mask;

employing the mask in a first logical AND operation and the complement of the mask in a second logical AND operations; and

deriving a result of the modular arithmetic operation by combining the results of the first and second logical AND operations in an OR operation.

24. At least one non-transitory machine-readable storage medium comprising instructions that when executed by a computing device, causes the computing device to:

digitally sign a message to create a signature using a modular arithmetic operation and a point multiplication operation, the modular arithmetic operation arranged to compensate for a value of a variable greater than a modulus without use of a branching instruction, the point multiplication operation arranged to prevent an instance of an infinite point without use of a branch instruction to compare a variable to zero, the point multiplication operation to comprise identifying a window size comprising a number of bits and an input variable comprising a first positive integer, converting the first positive integer to a second positive integer by performing operations including one or more bitwise shifts by the number of bits, and deriving a point on an elliptic curve based on the second positive integer; and

transmit the signature to a verifying server via a network.

25. The at least one non-transitory machine-readable storage medium of claim 24 , the modular arithmetic operation comprising modular negation.

26. The at least one non-transitory machine-readable storage medium of claim 24 , the computing device caused to perform the modular arithmetic operation by:

deriving a bitwise mask;

deriving a complement of the mask;

employing the mask in a first logical AND operation and the complement of the mask in a second logical AND operations; and

deriving a result of the modular arithmetic operation by combining the results of the first and second logical AND operations in an OR operation.

27. The at least one non-transitory machine-readable storage medium of claim 24 , the point multiplication operation arranged to generate a table comprising multiple entries, each entry comprising multiple bits, the bits of the multiple bits of each entry interspersed within the table to force a cache miss each time a portion of the table stored in a cache of a processor circuit of the computing device is accessed.

28. The at least one non-transitory machine-readable storage medium of claim 27 , the computing device caused to employ elliptic curve cryptography in digitally signing the message.