IP Library › Granted Patent US 9,500,740
Granted Patent B2
US 9,500,740 · App. 14/348,241 · Granted Nov 22, 2016

Receiver circuit, phased-array receiver and radar system

Inventor: Saverio Trotta (Munich, DE)
Assignee: Freescale Semiconductor, Inc.
G01S7/282G01S7/285H01Q3/34H03D7/1433H03D7/1458H03D7/165H03F1/0205H03F1/56H03F3/189H03F3/195H03F3/45085H03F3/60H04B1/16H03F2200/06H03F2200/09H03F2200/216H03F2200/222H03F2200/255H03F2200/294H03F2200/336H03F2200/411H03F2200/423H03F2200/555H03F2203/45544H03F2203/45554H03F2203/45594H03F2203/45596H03F2203/45622H03F2203/45631
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Quick Facts
Patent No.
US 9,500,740
App. No.
14/348,241
Filed
Mar 28, 2014
Granted
Nov 22, 2016
Kind
B2
Art Unit
3648
USPC
342/175
Abstract

A receiver circuit, comprises an input balun circuit comprising a balanced balun output and being capable of receiving RF signals, an input amplification circuit comprising a balanced amplifier input and a balanced amplifier output, a single balanced in-phase mixing circuit comprising a first unbalanced RF mixer input and a balanced in-phase mixing frequency input, and a single balanced quadrature mixing circuit comprising a second unbalanced RF mixer input and a balanced quadrature mixing frequency input. The balanced amplifier input is connected to the balanced balun output, a first terminal of the balanced amplifier output is connected to provide an amplified RF signal to the first unbalanced RF mixer input and a second terminal of the balanced amplifier output is connected to provide a phase-shifted amplified RF signal to the second unbalanced RF mixer input.

Claims (55)

1. A receiver circuit, comprising:

an input balun circuit comprising a balanced balun output and being capable of receiving RF signals, wherein balanced outputs are differential outputs, balanced inputs are differential inputs, and unbalanced inputs are single-ended inputs;

an input amplification circuit comprising:

a balanced amplifier input connected to the balanced balun output; and

a balanced amplifier output;

a single balanced in-phase mixing circuit comprising:

a first unbalanced RF mixer input; and

a balanced in-phase mixing frequency input; and

a single balanced quadrature mixing circuit comprising:

a second unbalanced RF mixer input; and

a balanced quadrature mixing frequency input;

wherein

a first terminal of said balanced amplifier output is connected to provide an amplified RF signal to said first unbalanced RF mixer input, the first terminal of said balanced amplifier output is not connected to the single balanced quadrature mixing circuit,

a second terminal of said balanced amplifier output is connected to provide a phase-shifted amplified RF signal to said second unbalanced RF mixer input, and the second terminal of said balanced amplifier output is not connected to the single balanced in-phase mixing circuit.

2. The receiver circuit as claimed in claim 1 , wherein said first terminal of said balanced amplifier output is connected to a first capacitive coupling device connected to a first transmission line connected to a second capacitive coupling device connected to said second terminal of said balanced amplifier output.

3. The receiver circuit as claimed in claim 2 , wherein said first transmission line is a half-wavelength transmission line.

4. The receiver circuit as claimed in claim 1 , wherein one or more of said single balanced in-phase mixing circuit and said single balanced quadrature mixing circuit comprises two transistors connected to form a common-emitter circuit.

5. The receiver circuit as claimed in claim 4 , wherein a control terminal of each of said two transistors is connected to a corresponding quarter-wavelength transmission line arranged to provide a common bias voltage.

6. The receiver circuit as claimed in claim 1 , wherein said single balanced in-phase mixing circuit comprises an in-phase IF output connected to provide an in-phase IF signal to a first filter circuit arranged to remove an in-phase mixing frequency portion from said in-phase IF signal.

7. The receiver as claimed in claim 6 , wherein said first filter circuit comprises at least a first quarter-wavelength transmission line and at least a first capacitive device.

8. The receiver circuit as claimed in claim 1 , wherein said single balanced quadrature mixing circuit comprises a quadrature IF output connected to provide a quadrature IF signal to a second filter circuit arranged to remove a quadrature mixing frequency portion from said quadrature IF signal.

9. The receiver circuit as claimed in claim 8 , wherein said second filter circuit comprises at least a second quarter-wavelength transmission line and at least a second capacitive device.

10. The receiver circuit as claimed in claim 1 , comprising a mixing frequency signal source connected to a 90° hybrid coupler comprising a first hybrid output connected to said balanced in-phase mixing frequency input, and a second hybrid output connected to said balanced quadrature mixing frequency input.

11. The receiver circuit as claimed in claim 10 , comprising one or more of a first fine tuning phase balancing circuit connected to said first hybrid output and a second fine tuning phase balancing circuit connected to said second hybrid output.

12. The receiver circuit as claimed in claim 11 , wherein one or more of said first and second fine tuning phase balancing circuits comprises a varactor circuit.

13. The receiver circuit as claimed in claim 1 , wherein said receiver circuit is a direct conversion receiver.

14. A phased array receiver, comprising:

a receiver circuit as claimed in claim 1 ; and

an antenna connected to an input terminal of the input balun circuit for receiving an incoming RF signal.

15. A radar system, comprising:

a receiver circuit as claimed in claim 1 ;

an antenna connected an input terminal of the input balun circuit for receiving a radar signal; and

a sender for radiating the radar signal.

16. A receiver circuit, comprising:

an input balun circuit comprising a balanced balun output and being capable of receiving RF signals, wherein balanced outputs are differential outputs, balanced inputs are differential inputs, and unbalanced inputs are single-ended inputs;

an input amplification circuit comprising:

a balanced amplifier input connected to the balanced balun output; and

a balanced amplifier output;

a single balanced in-phase mixing circuit comprising:

a first unbalanced RF mixer input; and

a balanced in-phase mixing frequency input;

a single balanced quadrature mixing circuit comprising:

a second unbalanced RF mixer input; and

a balanced quadrature mixing frequency input;

a mixing frequency signal source connected to a 90° hybrid coupler comprising:

a first hybrid output connected to the balanced in-phase mixing frequency input; and

a second hybrid output connected to the balanced quadrature mixing frequency input; and

one or more of a first fine tuning phase balancing circuit connected to the first hybrid output and a second fine tuning phase balancing circuit connected to the second hybrid output;

wherein

a first terminal of said balanced amplifier output is connected to provide an amplified RF signal to said first unbalanced RF mixer input, the first terminal of said balanced amplifier output is not connected to the single balanced quadrature mixing circuit,

a second terminal of said balanced amplifier output is connected to provide a phase-shifted amplified RF signal to said second unbalanced RF mixer input, and the second terminal of said balanced amplifier output is not connected to the single balanced in-phase mixing circuit.

17. The receiver circuit as claimed in claim 16 , wherein one or more of said first and second fine tuning phase balancing circuits comprises a varactor circuit.

18. The receiver circuit as claimed in claim 16 , wherein said first terminal of said balanced amplifier output is connected to a first capacitive coupling device connected to a first transmission line connected to a second capacitive coupling device connected to said second terminal of said balanced amplifier output.

19. The receiver circuit as claimed in claim 18 , wherein said first transmission line is a half-wavelength transmission line.

20. The receiver circuit as claimed in claim 16 , wherein one or more of said single balanced in-phase mixing circuit and said single balanced quadrature mixing circuit comprises two transistors connected to form a common-emitter circuit.

Assignments (26)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPLICATION NUMBERS 12222918, 14185362, 14147598, 14185868 & 14196276 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0479. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0498 →
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBERS PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0438. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded May 12, 2016
From: CITIBANK, NA
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038665/0136 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0479 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037458/0438 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0763 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0442 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032845/0522 →
SUPPLEMENT TO SECURITY AGREEMENT Recorded May 7, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 032845/0497 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2014
From: TROTTA, SAVERIO
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 032551/0330 →
Continuity (1)
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