Methods of operating sense amplifier circuits

1. A method of maintaining a voltage level of a bit line of a sense amplifier circuit, the method comprising:

providing a power supply voltage at a power supply node;

receiving the power supply voltage from the power supply node with an NMOS transistor;

maintaining a voltage level of the bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line;

receiving the voltage level of the bit line with a noise threshold control circuit;

inverting the voltage level with the noise threshold control circuit; and

driving a sense amplifier output with the noise threshold control circuit.

2. The method of claim 1 , wherein maintaining the voltage level of the bit line comprises controlling a gate of the NMOS transistor with the power supply voltage.

3. The method of claim 1 , wherein supplying sufficient current with the NMOS transistor to compensate a leakage current of the bit line comprises compensating current flow from a pass gate of a static random access memory (SRAM) or register circuit.

4. The method of claim 1 , further comprising pre-charging the bit line to a pre-charge voltage level below a power supply voltage value of the power supply voltage.

5. The method of claim 4 , wherein the pre-charge voltage level and the power supply voltage value differ by a value equal to a threshold voltage of the NMOS transistor.

6. A method of operating a sense amplifier circuit, the method comprising:

providing a power supply voltage at a power supply node;

receiving the power supply voltage from the power supply node with a first NMOS transistor;

maintaining a voltage level of a first bit line by supplying sufficient current with the first NMOS transistor to compensate a leakage current of the first bit line;

receiving the first voltage level of the first bit line with a noise threshold control circuit;

receiving a second voltage level of a second bit line with the noise threshold control circuit;

performing a NAND operation on the first voltage level and the second voltage level with the noise threshold control circuit; and

driving a sense amplifier output with the noise threshold control circuit.

7. The method of claim 6 , wherein maintaining the first voltage level of the first bit line comprises controlling a gate of the first NMOS transistor with the power supply voltage.

8. The method of claim 6 , wherein supplying sufficient current with the first NMOS transistor to compensate a leakage current of the first bit line comprises compensating current flow from a pass gate of a static random access memory (SRAM) or register circuit.

9. The method of claim 6 , wherein performing the NAND operation with the noise threshold control circuit comprises performing the NAND operation with a half-Schmitt trigger circuit.

10. The method of claim 6 , wherein performing the NAND operation with the noise threshold control circuit comprises performing the NAND operation with a Schmitt trigger circuit.

11. The method of claim 6 , further comprising maintaining the second voltage level of the second bit line by supplying sufficient current with a second NMOS transistor to compensate a leakage current of the second bit line.

12. The method of claim 6 , further comprising maintaining the second voltage level of the second bit line by supplying sufficient current with the first NMOS transistor to further compensate a leakage current of the second bit line.

13. The method of claim 6 , further comprising pre-charging at least one of the first bit line or the second bit line to a pre-charge voltage level below a power supply voltage value of the power supply voltage.

14. The method of claim 13 , wherein the pre-charge voltage level and the power supply voltage value differ by a value equal to a threshold voltage of the first NMOS transistor.

15. A method of operating a sense amplifier circuit, the method comprising:

providing a power supply voltage at a power supply node;

receiving the power supply voltage from the power supply node with an NMOS transistor;

maintaining a first voltage level of a first bit line by supplying sufficient current with the NMOS transistor to compensate a leakage current of the first bit line;

receiving the first voltage level of the first bit line with a NAND gate;

receiving a second voltage level of a second bit line with the NAND gate;

performing a NAND operation on the first voltage level and the second voltage level with the NAND gate;

driving a sense amplifier output with the NAND gate; and

lowering a trip point of the sense amplifier output with a threshold control circuit.

16. The method of claim 15 , wherein maintaining the first voltage level of the first bit line comprises controlling a gate of the NMOS transistor with the power supply voltage.

17. The method of claim 15 , wherein supplying sufficient current with the NMOS transistor to compensate a leakage current of the first bit line comprises compensating current flow from a pass gate of a static random access memory (SRAM) or register circuit.

18. The method of claim 15 , wherein lowering the trip point of the sense amplifier comprises effectively lowering a β value of the NAND gate with the threshold control circuit.

19. The method of claim 15 , further comprising pre-charging at least one of the first bit line or the second bit line to a pre-charge voltage level below a power supply voltage value of the power supply voltage.

20. The method of claim 19 , wherein the pre-charge voltage level and the power supply voltage value differ by a value equal to a threshold voltage of the NMOS transistor.