Methods of manufacturing semiconductor devices
Provided is a method of manufacturing a semiconductor device including: forming a gate electrode structure on an active region of a semiconductor substrate; forming recesses in regions positioned on both sides of the gate electrode structure on the active region; performing a pre-treatment on the recesses using an inert gas plasma; growing epitaxial layers for a source and a drain on the pre-treated recesses; and forming a source electrode structure and a drain electrode structure in the epitaxial layers for the source and the drain, respectively. Also provided is a method in which, after an etching process for forming recesses and/or after an etching process for forming a contact hole, an etched surface may be treated with an inert gas plasma before growing an epitaxial layer. Thus, one or two types of plasma treatment may be employed in the method.
1. A method of manufacturing a semiconductor device, the method comprising:
forming a gate electrode structure on an active region of a semiconductor substrate;
forming recesses in regions positioned on both sides of the gate electrode structure on the active region of the semiconductor substrate;
performing a pre-treatment on the recesses using an inert gas plasma to provide pre-treated recesses;
growing an epitaxial layer on the pre-treated recesses; and
forming an electrode structure on the epitaxial layer,
wherein performing the pre-treatment on the recesses comprises generating the inert gas plasma by applying power in a range of 800 kW to 4000 kW and the inert gas plasma includes at least one argon (Ar) and xenon (Xe).
2. The method of claim 1 , wherein the active region of the semiconductor substrate includes silicon or silicon germanium.
3. The method of claim 1 , wherein the epitaxial layer includes a silicon germanium epitaxial layer.
4. The method of claim 3 , wherein the silicon germanium epitaxial layer is doped with a p-type impurity.
5. The method of claim 1 , wherein the pre-treatment on the recesses is performed for a period of time in a range of 10 seconds to 300 seconds.
6. The method of claim 1 , wherein after forming the recesses in regions positioned on both sides of the gate electrode structure on the active region of the semiconductor substrate, residues remain on a surface of the recesses, and the method further comprises cleaning the residues before performing the pre-treatment on the recesses.
7. The method of claim 1 , further comprising, after performing the pre-treatment on the recesses,
oxidizing or nitrificating surfaces of the pre-treated recesses to provide oxidized or nitrificated surfaces, and
cleaning the oxidized or nitrificated surfaces.
8. The method of claim 1 , wherein the active region has an active fin structure having an upper surface and two opposing lateral surfaces, and the gate electrode structure intersects the active fin structure and is in contact with the upper surface and the two opposing lateral surfaces of the active fin structure.
9. The method of claim 1 , wherein the pretreatment is performed at a pressure in a range of 0.1 torr to 10 torr.
10. A method of manufacturing a semiconductor device, the method comprising:
forming a gate electrode structure on an active region of a semiconductor substrate;
forming recesses in regions positioned on both sides of the gate electrode structure on the active region of the semiconductor substrate;
growing a first epitaxial layer on the recesses;
forming an interlayer dielectric on the semiconductor substrate covering the active region of the semiconductor substrate and the first epitaxial layer;
forming a contact hole on the interlayer dielectric, to expose an area of the first epitaxial layer;
performing a pre-treatment on the exposed area of the first epitaxial layer with a first inert gas plasma to provide a pre-treated contact area of the first epitaxial layer;
growing a second epitaxial layer on the pre-treated contact area of the first epitaxial layer; and
forming an electrode structure on the second epitaxial layer,
wherein the first and second epitaxial layers include a silicon geranium epitaxial layer.
11. The method of claim 10 , further comprising, between forming the recesses and growing the first epitaxial layer, performing a pre-treatment on the recesses using a second inert gas plasma.
12. The method of claim 10 , wherein the active region of the semiconductor substrate includes silicon or silicon germanium.
13. The method of claim 10 , wherein the first epitaxial layer is Si 1-x Ge x and the second epitaxial layer is Si 1-y Ge y , wherein x and y have a value of 0<x<y<1.
14. The method of claim 10 , wherein forming the electrode structure comprises:
forming a silicide layer on the second epitaxial layer; and
filling the contact hole with an electrode material.
15. A method of preparing a semiconductor substrate for a selective epitaxial growth process, the method comprising:
providing a semiconductor substrate comprising a gate electrode structure and at least two recesses, the at least two recesses on opposing sides of the gate electrode structure;
pre-treating the at least two recesses with a first inert gas plasma to provide at least two pre-treated recesses; and
growing an epitaxial layer on the at least two pre-treated recesses,
wherein the pre-treating is performed at a pressure in a range of 0.1 torr to 10 torr and comprises applying power in a range of 800 kW to 4000 kW.
16. The method of claim 15 , wherein the inert gas plasma comprises helium, argon, and/or xenon.
17. The method of claim 15 , wherein the semiconductor substrate comprises silicon or silicon germanium.
18. The method of claim 15 , further comprising pre-treating a surface of the epitaxial layer with a second inert gas plasma.
19. The method of claim 18 , wherein pre-treating the surface of the epitaxial layer with the second inert gas plasma comprises applying power in a range of 800 kW to 4000 kW.
20. The method of claim 10 , wherein the pretreatment is performed at a pressure in a range of 0.1 torr to 10 torr.