IP Library Granted Patent US 9,508,809
Granted Patent B2
US 9,508,809 · App. 14/792,107 · Granted Nov 29, 2016

III-N device with extended source and drain

Inventor: Keiichi Matsushita (Tokyo, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/41766H01L29/66462H01L29/7786H01L29/2003
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Quick Facts
Patent No.
US 9,508,809
App. No.
14/792,107
Granted
Nov 29, 2016
Kind
B2
Abstract

A semiconductor device includes a substrate, a semiconductor layer having a buffer layer, a spacer layer, and barrier layer sequentially stacked on the substrate, and first and second ohmic electrodes installed on an upper surface of the barrier layer in the substrate to be separated from each other. Each of the first and second ohmic electrodes includes a portion formed on the upper surface of the barrier layer and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, and the portion formed on the upper surface of the barrier layer and the electrode portions are integrally formed.

Claims (15)

1. A semiconductor device comprising:

a substrate;

a semiconductor layer having a buffer layer, a spacer layer, and a barrier layer sequentially stacked on the substrate; and

first and second ohmic electrodes installed on an upper surface of the barrier layer to be separated from each other; and

a third electrode installed between the first and second ohmic electrodes on the upper surface of the barrier layer,

wherein each of the first and second ohmic electrodes includes:

a portion formed on the upper surface of the barrier layer; and

electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves,

wherein the portion and the electrode portions are integrally formed,

wherein a shape of an opening of each of the plurality of the grooves is rectangular,

wherein the plurality of the grooves are arranged in a direction perpendicular to a longitudinal direction of the opening of each of the grooves,

wherein the longitudinal direction of the opening of each of the grooves is perpendicular to an extending direction of the third electrode, and

wherein both long sides of the opening of each of the plurality of the grooves are formed in a saw teeth shape.

2. The semiconductor device according to claim 1 ,

wherein the first ohmic electrode is a source electrode, the second ohmic electrode is a drain electrode, and the third electrode is a gate electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2015
From: MATSUSHITA, KEIICHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 036264/0406 →
Priority Claims (1)
JP 2014-183586 · Sep 9, 2014 · national
Continuity (1)
Related Publication 20160071939A1 · Mar 10, 2016