Instruction merging optimization

1. A computer program product for implementing instruction optimization, the computer program product comprising:

a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

determining that at least two machine instructions of an instruction stream are eligible for optimization, the at least two machine instructions including a memory load instruction and a data processing instruction to process data based on the memory load instruction;

merging, by a processor, the at least two machine instructions into a single optimized internal instruction based on determining that the at least two machine instructions are eligible for optimization, wherein the single optimized internal instruction comprises a single stored rename register identifier; and

executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction,

wherein the single optimized internal instruction is stored in a single slot in an issue queue, and the executing comprises executing the memory load instruction followed by the data processing instruction.

2. The computer program product of claim 1 , wherein executing the single optimized internal instruction includes executing the single optimized internal instruction instead of executing at least two internal instructions corresponding to the at least two machine instructions.

3. The computer program product of claim 1 , wherein the method further comprises storing the single optimized internal instruction as a single instruction in the tangible storage medium, and

wherein executing the single optimized internal instruction further comprises generating at least two internal instructions corresponding to the at least two machine instructions and executing the at least two internal instructions in separate operations.

4. The computer program product of claim 1 , wherein the method further comprises storing the single optimized internal instruction as a single instruction in the tangible storage medium, and

wherein the instruction execution unit is configured to execute the single optimized internal instruction a first time to perform an operation corresponding to the first machine instruction and to execute the single optimized internal instruction a second time to perform an operation corresponding to the second machine instruction.

5. A computer system for optimizing instructions, the computer system comprising:

a processor including an instruction execution unit configured to execute instructions and an instruction optimization unit configured to optimize two or more instructions; and

memory to store two or more machine instructions to be executed by the instruction execution unit,

the computer system configured to perform a method comprising:

analyzing the two or more machine instructions from among a stream of instructions to be executed by the instruction execution unit, the two or more machine instructions including a memory load instruction and a data processing instruction to perform a data processing function based on the memory load instruction,

identifying the two or more machine instructions as being eligible for optimization,

merging the two or more machine instructions into a single optimized internal instruction, wherein the single optimized internal instruction comprises a single stored rename register identifier, and

executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction,

wherein the single optimized internal instruction is stored in a single slot in an issue queue, and the executing comprises executing the memory load instruction followed by the data processing instruction.

6. The computer system of claim 5 , wherein determining that the two or more machine instructions are eligible for optimization includes determining that a target destination of the memory load instruction is the same as an operand source location of the data processing instruction.

7. The computer system of claim 5 , wherein the processor is configured to perform register renaming by allocating a single target register to represent a result of both the first and second ones of the two or more machine instructions.

8. The computer system of claim 5 , wherein the processor is configured to generate the single optimized internal instruction to have stored therein only one representation of a target register of the two or more machine instructions.

9. The computer system of claim 8 , wherein the single stored rename register identifier that identifies a target register of the memory load instruction and a source register of the data processing instruction, and

executing the single optimized internal instruction further comprises:

selecting the target register of the memory load instruction as the source register of the data processing instruction.

10. The computer system of claim 5 , wherein the computer system is configured to execute the single optimized internal instruction instead of executing two or more internal instructions corresponding to the two or more machine instructions.

11. The computer system of claim 5 , wherein the method further comprises:

executing the optimized internal instruction in two or more separate operation cycles to execute the memory load function and the data processing function.

12. The computer system of claim 5 , wherein the execution unit is configured to execute the optimized internal instruction by generating two or more separate internal instructions corresponding to the two or more machine instructions and to execute each of the two or more separate internal instructions in separate operation cycles.

13. A computer program product for implementing instruction optimization, the computer program product comprising:

a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

determining that at least two machine instructions of an instruction stream are eligible for optimization, the at least two machine instructions including a memory load instruction and a data processing instruction to process data based on the memory load instruction;

merging, by a processor, the at least two machine instructions into a single optimized internal instruction based on determining that the at least two machine instructions are eligible for optimization, wherein the single optimized internal instruction comprises a single stored rename register identifier; and

executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction,

wherein the single optimized internal instruction is stored in a single slot in an issue queue, and the executing comprises executing the memory load instruction followed by the data processing instruction, and

wherein the instruction optimization unit is configured to identify the first and second machine instructions as being eligible for optimization by identifying a destination of the load instruction as being the same as a destination and an operand location of the data processing instruction.