Semiconductor device with air gap and method for fabricating the same
A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion.
1. A method for fabricating a semiconductor device, comprising:
forming a plurality of first conductive patterns over a substrate;
forming an insulation layer over an entire surface of the substrate including the first conductive patterns;
forming an open portion between the first conductive patterns by etching the insulation layer;
forming a sacrificial spacer over sidewalls of the open portion;
forming a second conductive pattern over the sacrificial spacer in a lower section of the open portion;
forming an ohmic contact layer over the second conductive pattern;
forming an air gap by removing the sacrificial spacer;
capping the air gap by forming a barrier layer over the ohmic contact layer; and
forming a third conductive pattern over the barrier layer to fill an upper section of the open portion,
wherein the capping of the air gap comprises:
forming a first barrier layer over the ohmic contact layer to cap the air gap; and
forming a second barrier layer over the first barrier layer,
wherein a portion of the first barrier layer that is formed over a top surface and sidewalls of the ohmic contact layer has a first thickness, and a portion of the first barrier layer that is formed over the sidewalls of the open portion over the air gap has a second thickness that is less than the first thickness.
2. The method of claim 1 , wherein the first barrier layer is formed by a physical vapor deposition in an ionized metal plasma (PVD-IMP) method.
3. The method of claim 1 , wherein the first barrier layer or the second barrier layer comprise titanium-containing materials.
4. The method of claim 1 , further comprising:
performing an annealing process to induce a phase change in the ohmic contact layer after the forming the air gap.
5. The method of claim 4 , wherein the ohmic contact layer includes cobalt silicide having a CoSi x phase (wherein x=about 0.1 to about 1.5), and wherein the causing a phase change in the ohmic contact layer further comprises:
changing, by the annealing process, the cobalt silicide having the CoSi x phase (wherein x=about 0.1 to about 1.5) into cobalt silicide having a CoSi 2 phase.
6. The method of claim 1 , wherein the plurality of first conductive patterns comprise a plurality of bit lines, and the second conductive pattern, the ohmic contact layer, and the third conductive pattern comprises a storage node contact plug.
7. The method of claim 1 , wherein the second conductive pattern comprises a silicon-containing material, and the third conductive pattern comprise a metal-containing material.
8. The method of claim 1 , further comprising:
forming a buried gate-type transistor, including a gate electrode buried in the substrate, before the forming of the plurality of first conductive patterns.
9. The method of claim 1 , further comprising:
forming a capacitor over the third conductive pattern.