FinFET structure and method for manufacturing thereof
Present disclosure provides a FinFET structure, including a plurality of fins, a gate, and a first dopant layer. The gate is disposed substantially orthogonal over the plurality of fins, covering a portion of a top surface and a portion of sidewalls of the plurality of fins. The first dopant layer covers the top surface and the sidewalls of a junction portion of a first fin, configured to provide dopants of a first conductive type to the junction portion of the first fin. The junction portion is adjacent to the gate.
1. A FinFET structure, comprising:
a plurality of fins;
a gate, disposed substantially orthogonal over the plurality of fins, covering a portion of a top surface and a portion of sidewalls of the plurality of fins;
a first dopant layer, covering the top surface and the sidewalls of a junction portion of a first fin, configured to provide dopants of a first conductive type to the junction portion of the first fin, wherein the junction portion is adjacent to the gate, and
a sidewall spacer, covering the first dopant layer over the junction portion.
2. The FinFET structure of claim 1 , further comprising a second dopant layer, covering a top surface and sidewalls of the junction portion of a second fin, configured to provide dopants of a second conductive type to the junction portion of the second fin.
3. The FinFET structure of claim 1 , further comprising a bi-layer, covering a top surface and sidewalls of the junction portion of a second fin, wherein the bi-layer comprises a first dopant layer and a diffusion barrier layer.
4. The FinFET structure of claim 1 , wherein the first dopant layer comprises borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glasses (BPSG), or the combinations thereof.
5. The FinFET structure of claim 1 , wherein a first dopant concentration in the first fin is uniformly distributed in proximity to the top surface and the sidewalls of the first fin.
6. The FinFET structure of claim 1 , wherein a thickness of the first dopant layer is in a range of from about 1 nm to about 8 nm.
7. The FinFET structure of claim 5 , wherein a difference between the first dopant concentration in proximity to the top surface of the junction portion and the first dopant concentration in proximity to the sidewall of the junction portion is below about 5%.
8. A MOS structure, comprising:
a first semiconductor fin; and
a metal gate covering a channel of the MOS structure,
wherein the first semiconductor fin comprises:
a regrown region; and
a lightly doped region between the regrown region and the metal gate,
wherein a first dopant concentration in proximity to a top surface of the lightly doped region is substantially the same as the first dopant concentration in proximity to a bottom sidewall of the lightly doped region.
9. The MOS structure of claim 8 , wherein a difference between the first dopant concentration in proximity to the top surface of the lightly doped region and the first dopant concentration in proximity to the sidewall of the lightly doped region is below about 5%.
10. The MOS structure of claim 8 , wherein the top surface and the sidewall of the lightly doped region are covered by a first dopant layer configured to provide the lightly doped region with dopants of a first conductive type.
11. The MOS structure of claim 10 , wherein the dopant layer comprises BSG, PSG, BPSG, or the combinations thereof.
12. The MOS structure of claim 10 , wherein a thickness of the first dopant layer is in a range of from about 1 nm to about 8 nm.
13. The MOS structure of claim 8 , further comprising a second semiconductor fin having a lightly doped region between a regrown region and the metal gate, wherein a second dopant concentration in proximity to a top surface of the lightly doped region is substantially the same as the second dopant concentration in proximity to a bottom sidewall of the lightly doped region.
14. The MOS structure of claim 13 , wherein a difference between the second dopant concentration in proximity to the top surface of the lightly doped region and the second dopant concentration in proximity to the sidewall of the lightly doped region is below about 5%.
15. A non-planar FET structure, comprising
a semiconductor fin;
a gate over the semiconductor fin;
a source at least partially in the semiconductor fin and disposed at one sides of the gate;
a sidewall spacer over the semiconductor fin, spacing the gate and the source; and
a dopant layer on a top surface of the semiconductor fin, laterally abutting the gate and being encapsulated by the sidewall spacer.
16. The non-planar FET structure of claim 15 , wherein the gate is a metal gate.
17. The non-planar FET structure of claim 15 , wherein the dopant layer comprises borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glasses (BPSG), or the combinations thereof.
18. The non-planar FET structure of claim 15 , wherein the sidewall spacer is composed of nitride materials.
19. The non-planar FET structure of claim 15 , further comprising a capping layer over the dopant layer, the capping layer being encapsulated by the sidewall spacer.
20. The non-planar FET structure of claim 15 , wherein the dopant layer is not in contact with the source.