Programmable input/output circuit
A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.
1. An apparatus comprising:
a processing system configured to generate first output signals directed to an external circuit, and further configured to receive first input signals;
an input/output (I/O) pad communicatively coupled with the processing system and configured to establish, at least in part, a link with an external circuit;
a programmable I/O circuit coupled between the I/O pad and the processing system, the programmable I/O circuit configured to generate a second output signal provided to the I/O pad, the programmable I/O circuit being further configured to provide the first input signal to the processing system; and
a programmable reset circuit configured to generate a programmable reset signal provided to the I/O pad, the programmable reset signal being capable of resetting a component of the external circuit.
2. The apparatus of claim 1 , wherein the programmable reset circuit includes a programmable external reset cell configured to generate the programmable reset signal, and wherein the programmable reset signal is capable of resetting a device core included in the external circuit.
3. The apparatus of claim 2 , wherein the programmable reset circuit further includes a first non-volatile memory element configured to store a polarity state associated with the programmable reset signal.
4. The apparatus of claim 3 , wherein the first non-volatile memory element is coupled to the programmable external reset cell, and wherein the programmable external reset cell is configured to generate the programmable reset signal having a polarity determined based on the polarity state stored in the first non-volatile memory element.
5. The apparatus of claim 3 , wherein the programmable reset circuit further comprises a second non-volatile memory element configured to store a programmable reset key configured to enable and disable the polarity state stored in the first non-volatile memory element.
6. The apparatus of claim 5 , wherein an output of the first non-volatile memory element and an output of the second non-volatile memory element are coupled to combinatorial logic, and wherein an output of the combinatorial logic determines a polarity of the programmable reset signal.
7. The apparatus of claim 1 , wherein the second output signal is generated by a plurality of output buffers included in the programmable I/O circuit, wherein the plurality of output buffers is configured to generate the second output signal based, at least in part, on a plurality of output enable signals comprising a first output enable signal and a second output enable signal.
8. The apparatus of claim 7 , wherein the plurality of output buffers comprises digital output buffers.
9. The apparatus of claim 1 further comprising an input buffer configured to receive a second input signal from the I/O pad, and further configured to generate the first input signal that is provided to the processing system.
10. The apparatus of claim 9 , wherein the input buffer is configured to generate the first input signal based, at least in part, on the second input signal and an input enable signal.
11. A method comprising:
receiving a first output signal at a first output buffer included in a plurality of output buffers, the first output signal being received from a processing system;
generating, using the plurality of output buffers, a second output signal based, at least in part, on a plurality of output enable signals; and
generating, using a programmable reset circuit, a programmable reset signal capable of resetting a component of an external component.
12. The method of claim 11 , wherein the external component comprises a component selected from the group consisting of: a central processing unit (CPU) core, a direct memory access (DMA) controller, a programmable digital block, and a programmable analog block.
13. The method of claim 11 , wherein the programmable reset signal is generated based, at least in part, on a polarity signal determined based on a polarity state stored in a first non-volatile memory element.
14. The method of claim 13 , wherein the generating of the polarity signal further comprises:
combining an output of the first non-volatile memory element with an output of a second non-volatile memory element that identifies a programmable reset key.
15. The method of claim 11 further comprising:
receiving a first input signal at the I/O pad; and
generating a second input signal based, at least in part, on an input enable signal and the first input signal.
16. A system comprising:
an external circuit including core architecture;
a processing system configured to generate first output signals directed to an external circuit, and further configured to receive first input signals;
an input/output (I/O) pad communicatively coupled with the processing system and configured to establish, at least in part, a link with an external circuit;
a programmable I/O circuit coupled between the I/O pad and the processing system, the programmable I/O circuit configured to generate a second output signal provided to the I/O pad, the programmable I/O circuit being further configured to provide the first input signal to the processing system; and
a programmable reset circuit configured to generate a programmable reset signal provided to the I/O pad, the programmable reset signal being capable of resetting a component of the external circuit.
17. The system of claim 16 , wherein the core architecture comprises a component selected from the group consisting of: a central processing unit (CPU) core, a direct memory access (DMA) controller, a programmable digital block, and a programmable analog block.
18. The system of claim 16 , wherein the programmable reset circuit includes a programmable external reset cell configured to generate the programmable reset signal, and wherein the programmable reset signal is capable of resetting a device core included in the external circuit.
19. The system of claim 18 , wherein the programmable reset circuit further includes a first non-volatile memory element configured to store a polarity state associated with the programmable reset signal.
20. The system of claim 19 , wherein the first non-volatile memory element is coupled to the programmable external reset cell, wherein the programmable external reset cell is configured to generate the programmable reset signal having a polarity determined based on the polarity state stored in the first non-volatile memory element, and wherein the programmable reset circuit further comprises a second non-volatile memory element configured to store a programmable reset key configured to enable and disable the polarity state stored in the first non-volatile memory element.