Adaptive patterning for panelized packaging
An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.
1. A device package comprising:
a semiconductor die unit that further comprises an outline misaligned with a device package outline;
an encapsulant overmolding the semiconductor die unit;
a build-up structure disposed over both the semiconductor die unit and the encapsulant, the build-up structure comprising:
a redistribution layer (RDL) comprising a first portion aligned with the semiconductor die unit and a second portion formed as an underbump metallization (UBM) via capture pad aligned with the semiconductor die unit, wherein the first portion of the RDL is vertically offset from the semiconductor die unit,
a first via aligned with a bond pad of the semiconductor die unit and disposed between the bond pad and the first portion of the RDL, and
a UBM pad aligned with the device package outline, wherein the UBM via capture pad is disposed over the UBM pad, and
a UBM via aligned with the semiconductor die unit, wherein the UBM via is disposed between the UBM pad and the UBM via capture pad so that at least a portion of the UBM via capture pad and the UBM pad are vertically offset and connected through the UBM via; and
an input/output (I/O) interconnect disposed over the UBM pad, wherein the I/O interconnect is aligned with the device package outline.
2. The device package of claim 1 , wherein the UBM via capture pad is not aligned with the device package outline.
3. The device package of claim 1 , wherein the RDL is a fan-out structure with respect to the semiconductor die unit.
4. The device package of claim 1 , wherein the misalignment of the outline of the semiconductor die unit and device package outline is measured with respect to a reference position of at least one feature on the semiconductor die unit and includes an x-y position or an orientation.
5. A device package comprising:
a semiconductor die unit comprising an outline misaligned with a device package outline;
an encapsulant overmolding the semiconductor die unit; and
a build-up structure disposed over both the semiconductor die unit and the encapsulant, the build-up structure comprising:
a redistribution layer (RDL) comprising a first portion aligned with the semiconductor die unit and a second portion aligned with the device package outline, wherein the first portion of the RDL is vertically offset from the semiconductor die unit,
an electrical connecting feature aligned with a bond pad of the semiconductor die unit and disposed between the bond pad and the first portion of the RDL, and
an underbump metallization (UBM) pad disposed over the RDL and aligned with the device package outline.
6. The device package of claim 5 , further comprising an input/output (I/O) interconnect disposed over the build-up structure, wherein the I/O interconnect is aligned with the device package outline.
7. The device package of claim 5 , wherein the second portion of the RDL comprises a UBM via capture pad.
8. The device package of claim 5 , wherein at least a portion of the UBM via capture pad and the UBM pad are connected through a via.
9. The device package of claim 5 , wherein the misalignment of the semiconductor die unit outline and the device package outline is measured with respect to a reference position of at least one feature on the semiconductor die unit and includes an x-y position or orientation different from the device package outline.
10. The device package of claim 5 , wherein the RDL is a fan-out structure with respect to the semiconductor die unit.
11. A device package comprising:
a semiconductor die unit misaligned with the device package;
an encapsulant overmolding the semiconductor die unit; and
a build-up structure disposed over the semiconductor die unit, the build-up structure comprising a redistribution layer (RDL) comprising a first portion aligned with a bond pad of the semiconductor die unit and a second portion aligned with the device package, wherein the first portion of the RDL is disposed over and is vertically offset from the bond pad of the semiconductor die unit by an electrical connecting feature.
12. The device package of claim 11 , wherein the RDL comprises a first capture pad, a second capture pad, and a trace.
13. The device package of claim 11 , wherein the RDL is a fan-out structure with respect to the semiconductor die unit.
14. The device package of claim 11 , further comprising:
the encapsulant overmolding at least five sides of the device package; and
the RDL disposed over the semiconductor die unit and the encapsulant overmolding.
15. The device package of claim 11 , further comprising an input/output (I/O) interconnect disposed over the build-up structure, wherein the I/O interconnect is aligned with the device package.