IP Library › Granted Patent US 9,520,385
Granted Patent B1
US 9,520,385 · App. 14/754,070 · Granted Dec 13, 2016

Package structure and method for forming same

Inventors: Hsien-Wei Chen (Hsin-Chu, TW); Kuo-Chuan Liu (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L25/105H01L21/565H01L23/3114H01L23/5384H01L25/50H01L2225/1058H01L2225/1088
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Quick Facts
Patent No.
US 9,520,385
App. No.
14/754,070
Granted
Dec 13, 2016
Kind
B1
Abstract

A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.

Claims (70)

1. A method comprising:

depositing a seed layer on a dielectric layer;

patterning a photoresist layer over the seed layer to form an opening;

forming a solder layer in the opening;

forming a conductive layer over the solder layer through a plating process;

attaching a semiconductor die on the dielectric layer;

forming a molding compound layer over the dielectric layer to form a bottom package, wherein the semiconductor die, the conductive layer and the solder layer are embedded in the molding compound layer;

applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;

applying a dielectric removal process to the dielectric layer until a surface of the solder layer is exposed; and

mounting a top package on the bottom package.

2. The method of claim 1 , further comprising:

prior to the step of attaching the semiconductor die on the dielectric layer, removing the photoresist layer.

3. The method of claim 1 , wherein:

the top package comprises a bump and the bump of the top package and the solder layer form a joint structure during the step of mounting the top package on the bottom package, and wherein a lower portion of the joint structure is surrounded by the seed layer.

4. The method of claim 1 , further comprising:

prior to the step of forming the conductive layer over the solder layer through the plating process, depositing a nickel layer on the solder layer.

5. The method of claim 4 , wherein:

the nickel layer has a thickness in a range from about 0.5 μm to about 2 μm.

6. A method comprising:

depositing a seed layer on a dielectric layer;

patterning a photoresist layer over the seed layer to form an opening;

forming a solder layer in the opening;

forming a nickel layer on and in contact with the solder layer;

plating a conductive material over the nickel layer;

removing remaining portions of the photoresist layer;

attaching a semiconductor die on the dielectric layer;

forming a molding compound layer over the dielectric layer to form a bottom package;

applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;

removing a portion of the dielectric layer to expose a surface of the solder layer; and

mounting a top package on the bottom package.

7. The method of claim 6 , further comprising:

prior to the step of attaching the semiconductor die on the dielectric layer, etching exposed portions of the seed layer.

8. The method of claim 6 , wherein:

the semiconductor die is embedded in the molding compound layer after the step of forming the molding compound layer over the dielectric layer.

9. The method of claim 6 , further comprising:

forming an interconnect structure over the molding compound layer.

10. The method of claim 9 , wherein:

the interconnect structure comprises a metal line and a redistribution layer.

11. The method of claim 9 , wherein:

the interconnect structure is on and in contact with the molding compound layer; and

the interconnect structure is electrically coupled to the semiconductor die.

12. The method of claim 9 , further comprising:

forming a plurality of bumps over the interconnect structure, wherein the plurality of bumps are electrically connected to the semiconductor die through the interconnect structure.

13. The method of claim 6 , further comprising:

placing a bump of the top package against the nickel layer and the solder layer; and

applying a reflow process to the top package and the bottom package to form a joint structure.

14. The method of claim 6 , further comprising:

forming the nickel layer through a deposition process.

15. The method of claim 14 , wherein:

the nickel layer is of a thickness in a range from about 0.5 μm to about 2 μm.

16. A method comprising:

depositing a seed layer on a dielectric layer;

patterning a photoresist layer over the seed layer to form a first opening and a second opening;

forming a first solder layer in the first opening and a second solder layer in the second opening;

plating a conductive material in the first opening and the second opening to form a first via and a second via;

attaching a semiconductor die on the dielectric layer;

forming a molding compound layer over the dielectric layer to form a bottom package, wherein the semiconductor die, the first via and the second via are embedded in the molding compound layer;

applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;

removing portions of the dielectric layer to expose the first solder layer and the second solder layer; and

mounting a top package on the bottom package, wherein bumps of the top package, the first solder layer and the second solder layer form a joint structure.

17. The method of claim 16 , further comprising:

forming a first nickel layer on the first solder layer; and

forming a second nickel layer on the second solder layer.

18. The method of claim 17 , wherein:

the first nickel layer is between and in contact with the first solder layer and the first via; and

the second nickel layer is between and in contact with the second solder layer and the second via.

19. The method of claim 16 , further comprising:

prior to the step of attaching the semiconductor die on the dielectric layer, removing remaining portions of the photoresist layer.

20. The method of claim 16 , wherein:

the semiconductor die is between the first via and the second via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2015
From: CHEN, HSIEN-WEI; LIU, KUO-CHUAN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 037063/0354 →