IP Library › Granted Patent US 9,521,739
Granted Patent B2
US 9,521,739 · App. 14/394,477 · Granted Dec 13, 2016

Printed circuit board and design method thereof

Inventor: Jianyong Fu (Guangdong, CN)
Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
H05K1/0215H01R4/34H05K1/0216H01R4/64H01R12/51H05K3/0005H05K3/3452H05K2201/10409
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Quick Facts
Patent No.
US 9,521,739
App. No.
14/394,477
Granted
Dec 13, 2016
Kind
B2
Abstract

A printed circuit board (PCB) is provided. From top to bottom, the PCB sequentially includes: a top layer; an upper solder resist layer; a wiring layer; a lower solder resist layer; a bottom layer; and a hole installation part disposed on the upper solder resist layer, the wiring layer, the lower solder resist layer, and the bottom layer. Wherein, the hole installation part includes a screw hole and a copper exposing region; a copper foil is disposed on the copper exposing region of the upper solder resist layer, the wiring layer, the lower solder resist layer, and the bottom layer; an area of the copper foil is not less than an area of the copper exposing region.

Claims (11)

1. A printed circuit board (PCB), from a top to a bottom, sequentially comprising:

a top layer;

an upper solder resist layer;

a wiring layer;

a lower solder resist layer;

a bottom layer; and

a hole installation part disposed on each of the top layer, the upper solder resist layer, the wiring layer, the lower solder resist layer, and the bottom layer;

wherein, the hole installation part includes a screw hole and a copper exposing region; a copper foil is disposed on the copper exposing region of each of the top layer, the upper solder resist layer, the wiring layer, the lower solder resist layer, and the bottom layer; an area of the copper foil is not less than an area of the copper exposing region; and

wherein, the copper foil is disposed on a surface of each of the top layer, the upper solder resist layer, the wiring layer, the lower solder resist layer, and the bottom layer, and the copper foil does not disposed at an inner side wall of each of the top layer, the upper solder resist layer, the wiring layer, the lower solder resist layer, and the bottom layer.

2. The PCB according to claim 1 , wherein, the area of the copper foil is equal to the area of the copper exposing region.

3. The PCB according to claim 1 , wherein, a diameter of the copper exposing region is greater than a diameter of the screw hole by at least 0.2 mm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: FU, JIANYONG
To: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 033988/0569 →
Priority Claims (1)
CN 2014 1 0407289 · Aug 8, 2014 · national
Continuity (1)
Related Publication 20160050747A1 · Feb 18, 2016