IP Library Granted Patent US 9,524,925
Granted Patent B2
US 9,524,925 · App. 15/097,093 · Granted Dec 20, 2016

Method of manufacturing a semiconductor device

Inventors: Satoru Wakiyama (Kanagawa, JP); Masaki Okamoto (Kumamoto, JP); Yutaka Ooka (Kanagawa, JP); Reijiroh Shohji (Tokyo, JP); Yoshifumi Zaizen (Kanagawa, JP); Kazunori Nagahata (Kanagawa, JP); Masaki Haneda (Kanagawa, JP)
Assignee: Sony Corporation
H01L23/481H01L21/30604H01L21/31111H01L21/76877H01L21/76898H01L24/32H01L24/83H01L25/0657H01L25/50H01L27/1469H01L27/14632H01L27/14634H01L27/14636H01L27/14687H01L2224/32145H01L2225/06541
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Quick Facts
Patent No.
US 9,524,925
App. No.
15/097,093
Granted
Dec 20, 2016
Kind
B2
Abstract

There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.

Claims (18)

1. A method of manufacturing a semiconductor device including a through electrode that penetrates a first semiconductor base substrate, the method comprising:

forming an insulation layer that surrounds a circumference of a position at which the through electrode is formed, on a first surface of the first semiconductor base substrate;

bonding a second semiconductor base substrate to a first surface side of the first semiconductor base substrate;

forming an opening portion that penetrates from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate within a range surrounded by the insulation layer; and

forming the through electrode inside the opening portion.

2. The method of manufacturing a semiconductor device according to claim 1 , further comprising:

etching the first semiconductor base substrate within the range surrounded by the insulation layer, and then etching the first semiconductor base substrate remaining in an inner wall surface of the insulation layer in the step of forming the opening portion.

3. The method of manufacturing a semiconductor device according to claim 1 , comprising:

forming a first conductive layer in a wiring layer on the first surface of the first semiconductor base substrate,

wherein, as part of forming the opening portion, an opening portion is formed in the first conductive layer such that an opening on the second surface side of the first semiconductor base substrate is large and an opening on the first surface side of the first semiconductor base substrate is small.

4. The method of manufacturing a semiconductor device according to claim 1 , comprising:

selectively etching the first semiconductor base substrate in the range surrounded by the insulation layer; and

etching a part of an inner surface side of the insulation layer.

5. The method of manufacturing a semiconductor device according to claim 1 , comprising:

forming a first conductive layer in a wiring layer on the first surface of the first semiconductor base substrate, and forming an electrode protective layer between the insulation layer and the first conductive layer,

wherein forming the opening portion includes a step of etching the first semiconductor base substrate in the range surrounded by the insulation layer and a step of etching the portion from the electrode protective layer to the wiring layer on the second semiconductor base substrate.

6. The method of manufacturing a semiconductor device according to claim 5 , wherein, in forming the electrode protective layer, the electrode protective layer is formed such that the edge portion on an opening side of the electrode protective layer protrudes more in a center direction of the opening portion than the edge portion on an opening side of the insulation layer.

7. The method of manufacturing a semiconductor device according to claim 5 , wherein the electrode protective layer and the first conductive layer are formed in conjunction with the wiring layer on the first surface of the first semiconductor base substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2020
From: WAKIYAMA, SATORU; OKAMOTO, MASAKI; OOKA, YUTAKA; SHOHJI, REIJIROH; ZAIZEN, YOSHIFUMI; NAGAHATA, KAZUNORI; HANEDA, MASAKI
To: SONY CORPORATION
Reel/Frame 053697/0320 →
Priority Claims (2)
JP 2012-147316 · Jun 29, 2012 · national
JP 2013-024505 · Feb 12, 2013 · national
Continuity (2)
Division 14409634
Related Publication 20160247746A1 · Aug 25, 2016