IP Library › Granted Patent US 9,525,020
Granted Patent B2
US 9,525,020 · App. 14/249,945 · Granted Dec 20, 2016

Semiconductor device and method for forming the same

Inventors: Chung-Ren Lao (Taichung, TW); Hsing-Chao Liu (Jhudong Township, TW); Tzung-Hsian Wu (Kaohsiung, TW); Chih-Jen Huang (Dongshan Township, TW)
Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
H01L28/60H01L21/28052H01L27/0629H01L27/1085H01L28/20H01L29/4933H01L29/665
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Quick Facts
Patent No.
US 9,525,020
App. No.
14/249,945
Granted
Dec 20, 2016
Kind
B2
Abstract

A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed.

Claims (34)

1. A semiconductor device, comprising:

a substrate having an isolation structure therein;

a capacitor disposed on the isolation structure and comprising:

a polysilicon electrode;

an insulating layer disposed on the polysilicon electrode; and

a metal electrode disposed on the insulating layer;

a polysilicon layer disposed on the isolation structure; and

a resistor disposed on the polysilicon layer and comprising an another metal electrode, wherein the insulating layer extends between the another metal electrode and the polysilicon layer, and a top surface of the polysilicon electrode is below a bottom surface of the another metal electrode over the insulating layer.

2. The semiconductor device as claimed in claim 1 , wherein the polysilicon electrode comprises a silicide layer adjacent to the top surface of the polysilicon electrode.

3. The semiconductor device as claimed in claim 2 , wherein the silicide layer comprises cobalt silicide, titanium silicide or tungsten silicide.

4. The semiconductor device as claimed in claim 1 , wherein the metal electrode comprises titanium nitride, tantalum nitride or a copper aluminum alloy.

5. The semiconductor device as claimed in claim 1 , wherein the metal electrode has a thickness in a range of 200 Å to 800 Å.

6. The semiconductor device as claimed in claim 1 , wherein the insulating layer comprises an oxynitride layer, an oxide layer, oxide-nitride-oxide stacked layers or high k dielectric material layers.

7. The semiconductor device as claimed in claim 1 , wherein the isolation structure is a shallow trench isolation structure.

8. The semiconductor device as claimed in claim 1 , further comprising:

a first contact disposed on and electrically connected to the metal electrode; and

a second contact disposed on the polysilicon electrode and penetrating the insulating layer to be electrically connected to the polysilicon electrode.

9. The semiconductor device as claimed in claim 1 , wherein the bottom surface of the another metal electrode over the insulating layer is above a bottom surface of the metal electrode.

10. A method for forming a semiconductor device, comprising:

providing a substrate having an isolation structure therein;

forming a polysilicon electrode and a polysilicon layer on the isolation structure;

forming an insulating layer on the polysilicon electrode and the polysilicon layer; and

forming a metal electrode and an another metal electrode on the insulating layer, wherein a capacitor is composed of the polysilicon electrode, the insulating layer and the metal electrode over the polysilicon electrode, and a resistor comprises the another metal electrode over the polysilicon layer, and wherein a top surface of the polysilicon electrode is below a bottom surface of the another metal electrode over the insulating layer.

11. The method as claimed in claim 10 , wherein the step of forming the polysilicon electrode comprises forming a silicide layer adjacent to a top surface of the polysilicon electrode.

12. The method as claimed in claim 11 , wherein the silicide layer comprises cobalt silicide, titanium silicide or tungsten silicide.

13. The method as claimed in claim 10 , wherein the metal electrode comprises titanium nitride, tantalum nitride or a copper aluminum alloy.

14. The method as claimed in claim 10 , wherein the metal electrode has a thickness in a range of 200 Å to 800 Å.

15. The method as claimed in claim 10 , wherein the insulating layer comprises an oxynitride layer, an oxide layer, oxide-nitride-oxide stacked layers or high k dielectric material layers.

16. The method as claimed in claim 10 , wherein the isolation structure is a shallow trench isolation structure.

17. The method as claimed in claim 10 , further comprising:

forming a first contact on the metal electrode to be electrically connected thereto; and

forming a second contact on the polysilicon electrode to be electrically connected thereto, wherein the second contact penetrates the insulating layer.

18. The method as claimed in claim 10 , wherein the bottom surface of the another metal electrode over the insulating layer is above a bottom surface of the metal electrode.

19. The semiconductor device as claimed in claim 8 , wherein the metal electrode is sandwiched between the insulating layer and the first contact.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2014
From: LAO, CHUNG-REN; LIU, HSING-CHAO; WU, TZUNG-HSIAN; HUANG, CHIH-JEN
To: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
Reel/Frame 032653/0278 →
Continuity (1)
Related Publication 20150295018A1 · Oct 15, 2015