Display substrates, methods of manufacturing the same and display devices including the same
A display substrate includes a base substrate, a switching device on the base substrate and an alignment pattern. The switching device includes an active pattern, a gate insulation layer pattern partially covering the active pattern, a gate electrode on the gate insulation layer pattern, and a source electrode and a drain electrode electrically connected to the active pattern. The alignment pattern has a multi-layered structure and is spaced apart from the switching device on the base substrate. The alignment pattern includes materials which have different transmittances.
1. A display substrate, comprising:
a base substrate;
a switching device disposed on the base substrate, the switching device comprising:
an active pattern;
a gate insulation layer pattern partially covering the active pattern;
a gate electrode disposed on the gate insulation layer pattern; and
a source electrode and a drain electrode electrically connected to the active pattern; and
an alignment pattern comprising a multi-layered structure and being spaced apart from the switching device on the base substrate, the alignment pattern comprising materials which have different transmittances.
2. The display substrate of claim 1 , wherein the active pattern comprises an oxide semiconductor.
3. The display substrate of claim 2 , wherein a lowermost layer of the alignment pattern has a transmittance lower than that of the active pattern.
4. The display substrate of claim 3 , wherein an uppermost layer of the alignment pattern comprises a same material as that of the active pattern.
5. The display substrate of claim 1 , further comprising a first dummy pattern and a first buffer layer pattern sequentially disposed between the base substrate and the active pattern.
6. The display substrate of claim 5 , wherein the alignment pattern comprises a second dummy pattern, a second buffer layer pattern, and a dummy active pattern sequentially disposed on the base substrate.
7. The display substrate of claim 6 , wherein the active pattern and the dummy active pattern comprise an oxide semiconductor.
8. The display substrate of claim 6 , wherein the first dummy pattern and the second dummy pattern comprise a silicon compound or a metal.
9. The display substrate of claim 6 , wherein the first buffer layer pattern and the second buffer layer pattern comprise at least one material selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride.
10. The display substrate of claim 1 , wherein the base substrate comprises a display region and a wiring region,
the switching device is disposed on the display region of the base substrate, and
the alignment pattern is disposed on the wiring region of the base substrate.
11. The display substrate of claim 10 , further comprising an insulating interlayer disposed on both the display region and the wiring region, the insulating layer covering the switching device and the alignment pattern.
12. The display substrate of claim 11 , further comprising:
a lower electrode disposed on the display region of the base substrate; and
an upper electrode disposed on the insulating interlayer, the upper electrode superimposed over the lower electrode.
13. The display substrate of claim 11 , further comprising a pad disposed on a portion of the insulating interlayer on the wiring region.
14. The display substrate of claim 11 , further comprising:
a via insulation layer covering the source electrode and the drain electrode on the insulating interlayer; and
a pixel electrode disposed on the via insulation layer, the pixel electrode configured to electrically connect to the switching device.
15. A display device, comprising:
a base substrate comprising a first region and a second region;
a switching device disposed on the first region of the base substrate;
an alignment pattern disposed on the second region of the base substrate, the alignment pattern comprising a lower pattern and an upper pattern, the upper pattern having a transmittance greater than that of the lower pattern;
a pixel electrode configured to electrically connect to the switching device on the first region;
a display layer disposed on the pixel electrode; and
an opposing electrode disposed facing the pixel electrode with respect to the display layer.
16. The display device of claim 15 , wherein the upper pattern comprises an oxide semiconductor, and the lower pattern comprises a silicon compound or a metal, and
the alignment pattern further comprises a buffer layer pattern disposed between the upper pattern and the lower pattern, the buffer layer pattern comprising an insulative material.