IP Library › Granted Patent US 9,529,645
Granted Patent B2
US 9,529,645 · App. 14/635,790 · Granted Dec 27, 2016

Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code

Inventors: Suresh Srinivas (Portland, OR); Stephen H. Dohrmann (Hillsboro, OR); Mingqiu Sun (Beaverton, OR); Uma Srinivasan (Sunnyvale, CA); Ravi Rajwar (Portland, OR); Konrad K. Lai (Vancouver, WA)
Assignee: Intel Corporation
G06F9/528G06F9/45516G06F9/526G06F8/458G06F9/3842G06F17/30168G06F17/30362Y10S707/99938
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Quick Facts
Patent No.
US 9,529,645
App. No.
14/635,790
Granted
Dec 27, 2016
Kind
B2
Abstract

Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.

Claims (33)

1. A method to control a lock of an object, comprising:

intercepting, by executing an instruction with a processor, a request to apply the lock on the object;

identifying, by executing an instruction with the processor, a performance history of the object based on a number of instances of contention;

reducing computing resources of the processor by, when the number of instances satisfies a threshold:

generating, by executing an instruction with the processor, a lock bypass for the object to cause speculative execution of target code within the object; and

reducing, by executing an instruction with the processor, an execution time of the speculative execution by diverting the speculative execution of the target code from a managed runtime environment (MRE) to the processor; and

preventing, by executing an instruction with the processor, speculative execution by applying the lock on the object when the number of instances does not satisfy the threshold.

2. A method as defined in claim 1 , further including identifying a type of instruction set architecture (ISA) associated with the processor.

3. A method as defined in claim 2 , further including invoking a status register query associated with the type of ISA when the object is contended.

4. A method as defined in claim 2 , further including invoking a profiling instruction associated with the type of ISA when the object is contended, the profiling instruction to identify error register fault codes.

5. A method as defined in claim 1 , further including generating a forecaster table containing identifiers of respective objects having the number of instances satisfying the threshold.

6. A method as defined in claim 5 , further including preventing speculative execution of the respective objects in the forecaster table in response to detecting the request to apply the lock.

7. An apparatus to control a lock of an object, comprising:

a bypass code shell builder to:

intercept a request to apply the lock on the object;

identify a performance history of the object based on a number of instances of contention;

a lock bypass manager to reduce computing resources of a processor by, when the number of instances satisfies a threshold, generating a lock bypass for the object to cause speculative execution of target code within the object; and

an instruction set architecture (ISA) identifier to reduce an execution time of the speculative execution by diverting the speculative execution of the target code from a managed runtime environment (MRE) to the processor, the lock bypass manager to prevent speculative execution by applying the lock on the object when the number of instances does not satisfy the threshold, at least one of the bypass code shell builder, the lock bypass manager, or the ISA identifier including the processor.

8. An apparatus as defined in claim 7 , wherein the ISA identifier is to identify a type of ISA associated with the processor.

9. An apparatus as defined in claim 8 , wherein the ISA identifier is to invoke a status register query associated with the type of ISA when the object is contended.

10. An apparatus as defined in claim 8 , wherein the ISA identifier is to invoke a profiling instruction associated with the type of ISA when the object is contended, the profiling instruction to identify error register fault codes.

11. An apparatus as defined in claim 7 , further including an object lock tester to generate a forecaster table containing identifiers of respective objects having the number of instances satisfying the threshold.

12. A tangible computer readable hardware storage device or storage disk comprising instructions to control a lock of an object, wherein the instructions, when executed, cause a processor to, at least:

intercept a request to apply the lock on the object;

identify a performance history of the object based on a number of instances of contention;

reduce computing resources of the processor by, when the number of instances satisfies a threshold, generating a lock bypass for the object to cause speculative execution of target code within the object;

reduce an execution time of the speculative execution by diverting the speculative execution of the target code from a managed runtime, environment (MRE) to the processor; and

prevent speculative execution by applying the lock on the object when the number of instances does not satisfy the threshold.

13. A hardware storage device or storage disk as defined in claim 12 , wherein the instructions, when executed, cause the processor to identify a type of instruction set architecture (ISA) associated with the processor.

14. A hardware storage device or storage disk as defined in claim 13 , wherein the instructions, when executed, cause the processor to invoke a status register query associated with the type of ISA when the object is contended.

15. A hardware storage device or storage disk as defined in claim 13 , wherein the instructions, when executed, cause the processor to invoke a profiling instruction associated with the type of ISA when the object is contended, the profiling instruction to identify error register fault codes.

16. A hardware storage device or storage disk as defined in claim 12 , wherein the instructions, when executed, cause the processor to generate a forecaster table containing identifiers of respective objects having the number of instances satisfying the threshold.

17. A hardware storage device or storage disk as defined in claim 16 , wherein the instructions, when executed, cause the processor to prevent speculative execution of the respective objects in the forecaster table in response to detecting the request to apply the lock.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2015
From: SRINIVAS, SURESH; DOHRMANN, STEPHEN H.; SRINIVASAN, UMA; SUN, MINGQUI; RAJWAR, RAVI; LAI, KONRAD K.
To: INTEL CORPORATION
Reel/Frame 035367/0462 →
Continuity (2)
Continuation 12645668 · Dec 23, 2009
Related Publication 20150169384A1 · Jun 18, 2015