False-trigger free power-rail ESD clamp protection circuit

1. A false-trigger free power-rail ESD clamp protection circuit, wherein the circuit comprises an ESD impact detection component, a discharge transistor, a discharge transistor turn-on channel, and a discharge transistor shutoff channel; the ESD impact detection component comprises NMOS transistors (Mcn 1 ) and (Mcn 2 ), a capacitor (C 1 ) and a resistor (R 1 ); the discharge transistor is a NMOS transistor (Mbig); the discharge transistor turn-on channel comprises PMOS transistors (Mp 2 - 1 ), (Mp 2 - 2 ) and (Mp 3 ) and an NMOS transistor (Mn 2 ); and the discharge transistor shutoff channel comprises PMOS transistors (Mp 4 ), (Mp 5 ) and (Mp 6 ), NMOS transistors (Man 1 ), (Man 2 ), (Mbn 1 ), (Mbn 2 ), (Mn 3 ), (Mn 4 - 1 ) and (Mn 4 - 2 ), and capacitors (C 2 ) and (C 3 ).

2. The false-trigger free power-rail ESD clamp protection circuit according to claim 1 , wherein in the ESD impact detection component, a gate of the NMOS transistor (Mcn 1 ) is connected with a lower electrode plate of the capacitor (C 1 ), an upper electrode plate of the capacitor (C 1 ) is connected with a power supply (VDD) of the false-trigger free power-rail ESD clamp protection circuit, a source of the NMOS transistor (Mcn 1 ) is connected with end (A) of the resistor (R 1 ), end (B) of the resistor (R 1 ) is grounded, a drain of the NMOS transistor (Mcn 1 ) is connected with the lower electrode plate of the capacitor (C 1 ), a gate of the NMOS transistor (Mcn 2 ) is connected with the lower electrode plate of the capacitor (C 1 ), a source of the NMOS transistor (Mcn 2 ) is connected with end (A) of the resistor (R 1 ), and a drain of the NMOS transistor (Mcn 2 ) is connected with the power supply VDD of the false-trigger free power-rail ESD clamp protection circuit;

a source of the NMOS transistor (Mbig) is grounded, and a drain of the NMOS transistor (Mbig) is connected with the power supply (VDD) of the false-trigger free power-rail ESD clamp protection circuit;

in the discharge transistor turn-on channel, a gate of the PMOS transistor (Mp 2 - 1 ) is connected with end (A) of the resistor (R 1 ), a source of the PMOS transistor (Mp 2 - 1 ) is connected with a gate of the PMOS transistor (Mp 2 - 2 ), a source of the PMOS transistor (Mp 2 - 2 ) is connected with the power supply (VDD) of the false-trigger free power-rail ESD clamp protection circuit, a drain of the PMOS transistor (Mp 2 - 2 ) is connected with the source of the PMOS transistor (Mp 2 - 1 ), a drain of the PMOS transistor (Mp 2 - 1 ) is connected with a gate of the PMOS transistor (Mp 3 ), a source of the PMOS transistor (Mp 3 ) is connected with the power supply (VDD) of the false-trigger free power-rail ESD clamp protection circuit, a drain of the PMOS transistor (Mp 3 ) is connected with a gate of the discharge transistor (Mbig), a gate of the NMOS transistor (Mn 2 ) is connected with end (A) of the resistor (R 1 ), a source of the NMOS transistor (Mn 2 ) is grounded, and a drain of the NMOS transistor (Mn 2 ) is connected with the gate of the PMOS transistor (Mp 3 );

in the discharge transistor shutoff channel, a gate of the PMOS transistor (Mp 4 ) is connected with a drain of the PMOS transistor (Mp 5 ), a gate of the PMOS transistor (Mp 5 ) is connected with end (A) of the resistor (R 1 ), a source of the PMOS transistor (Mp 5 ) is connected with the power supply (VDD) of the false-trigger free power-rail ESD clamp protection circuit, a source of the PMOS transistor (Mp 4 ) is connected with the power supply (VDD) of the false-trigger free power-rail ESD clamp protection circuit, a drain of the PMOS transistor (Mp 4 ) is connected with a gate of the PMOS transistor (Mp 6 ), a source of the PMOS transistor (Mp 6 ) is connected with the power supply (VDD) of the false-trigger free power-rail ESD clamp protection circuit, a drain of the PMOS transistor (Mp 6 ) is connected with a gate of the NMOS transistor (Mn 3 ), a source of the NMOS transistor (Mn 3 ) is grounded, a drain of the NMOS transistor (Mn 3 ) is connected with a gate of the discharge transistor (Mbig), a gate of the NMOS transistor (Man 1 ) is connected with a lower electrode plate of the capacitor (C 2 ), an upper electrode plate of the capacitor (C 2 ) is connected with a drain of the PMOS transistor (Mp 5 ), a source of the NMOS transistor (Man 1 ) is grounded, a drain of the NMOS transistor (Man 1 ) is connected with the lower electrode plate of the capacitor (C 2 ), a gate of the NMOS transistor (Man 2 ) is connected with the lower electrode plate of the capacitor (C 2 ), a source of the NMOS transistor (Man 2 ) is grounded, a drain of the NMOS transistor (Man 2 ) is connected with the upper electrode plate of the capacitor (C 2 ), a gate of the NMOS transistor (Mbn 1 ) is connected with the lower electrode plate of the capacitor (C 3 ) an upper electrode plate of the capacitor (C 3 ) is connected with a drain of the PMOS transistor (MP 6 ), a source of the NMOS transistor (Mbn 1 ) is grounded, a drain of the NMOS transistor (Mbn 1 ) is connected with the lower electrode plate of the capacitor (C 3 ) a gate of the NMOS transistor (Mbn 2 ) is connected with the lower electrode plate of the capacitor (C 3 ), a source of the NMOS transistor (Mbn 2 ) is grounded, a drain of the NMOS transistor (Mbn 2 ) is connected with the upper electrode plate of the capacitor (C 3 ) a gate of the NMOS transistor (Mn 4 - 1 ) is connected with the upper electrode plate of the capacitor (C 2 ), a source of the NMOS transistor (Mn 4 - 1 ) is connected with a gate of the NMOS transistor (Mn 4 - 2 ), a source of the NMOS transistor (Mn 4 - 2 ) is grounded, a drain of the NMOS transistor (Mn 4 - 2 ) is connected with a source of the NMOS transistor (Mn 4 - 1 ), and a drain of the NMOS transistor (Mn 4 - 1 ) is connected with the gate of the PMOS transistor (Mp 6 ).

3. The false-trigger free power-rail ESD clamp protection circuit according to claim 1 , wherein the ESD impact detection component identifies whether an impact applied between a power supply wire and a ground wire is an ESD impact; when the impact is the ESD impact, a corresponding signal is sent to turn on the discharge transistor, and when the circuit is normally powered up, the discharge transistor is shut off; the discharge transistor provides a low-resistance discharge channel for electrostatic charge brought about when the ESD impact occurs; the discharge transistor turn-on channel turns on the discharge transistor according to an identification signal provided by the ESD impact detection component when the ESD impact occurs; the discharge transistor shutoff channel provides sufficient time delay for the turn-on state of the discharge transistor after the discharge transistor turn-on channel turns on the discharge transistor, thus ensuring that the discharge transistor is shut off after the electrostatic charge is completely discharged.

4. The false-trigger free power-rail ESD clamp protection circuit according to claim 2 , wherein the ESD impact detection component identifies whether an impact applied between a power supply wire and a ground wire is an ESD impact; when the impact is the ESD impact, a corresponding signal is sent to turn on the discharge transistor, and when the circuit is normally powered up, the discharge transistor is shut off; the discharge transistor provides a low-resistance discharge channel for electrostatic charge brought about by the impact when ESD impact occurs; the discharge transistor turn-on channel turns on the discharge transistor according to an identification signal provided by the ESD impact detection component when the ESD impact occurs; the discharge transistor shutoff channel provides sufficient time delay for the turn-on state of the discharge transistor after the discharge transistor turn-on channel turns on the discharge transistor, thus ensuring that the discharge transistor is shut off after the electrostatic charge is completely discharged.

5. A false-trigger free power-rail ESD clamp protection circuit, wherein the circuit comprises:

an ESD impact detection component which generates an impact identification signal when an ESD impact occurs, and includes a first capacitor, a first resistor and at least two first transistors disposed in a first current mirror structure;

a discharge transistor;

a discharge transistor turn-on channel which turns on the discharge transistor when the impact identification signal is received from the ESD impact detection component;

and a discharge transistor shutoff channel that provides a time delay for a shutoff state of the discharge transistor after the discharge transistor turn-on channel turns on the discharge transistor.

6. The false-trigger free power-rail ESD clamp protection circuit of claim 5 , wherein the at least two first transistors are NMOS transistors.

7. The false-trigger free power-rail ESD clamp protection circuit of claim 6 , wherein the discharge transistor is a NMOS transistor.

8. The false-trigger free power-rail ESD clamp protection circuit of claim 7 , wherein the discharge transistor has a turn-on time which is out of a control of a detection capacitance resistance time constant.

9. The false-trigger free power-rail ESD clamp protection circuit of claim 8 , wherein the detection capacitance resistance time constant is a product of a capacitance value of the first capacitor and a resistance value of the first resistor.

10. The false-trigger free power-rail ESD clamp protection circuit of claim 5 , wherein the time delay is sufficient enough to ensure that the discharge transistor is shut off after an electrostatic charge is completely discharged.

11. The false-trigger free power-rail ESD clamp protection circuit of claim 5 ,

wherein the discharge transistor turn-on channel comprises at least 3 PMOS transistors and an NMOS transistor,

wherein the discharge transistor shutoff channel comprises at least two passive capacitors, at least 3 PMOS transistors, at least two second NMOS transistors disposed in a second current mirror structure, at least two third NMOS transistors disposed in a third current mirror structure, and

wherein the second and third current mirror structures increase a time delay of the discharge transistor shutoff channel such that an output of the ESD impact detection component requires a smaller voltage value to turn on the discharge transistor shutoff channel.