IP Library › Granted Patent US 9,531,332
Granted Patent B2
US 9,531,332 · App. 14/655,217 · Granted Dec 27, 2016

Distortion-compensation device and distortion-compensation method

Inventors: Yoshito Hirai (Kanagawa, JP); Kouji Okamoto (Osaka, JP)
Assignee: PANASONIC CORPORATION
H03F1/3247H03F3/189H03F3/19H03F3/24H04B1/0475H03F2200/451H03F2201/3224H04B2001/0425
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Quick Facts
Patent No.
US 9,531,332
App. No.
14/655,217
Granted
Dec 27, 2016
Kind
B2
Abstract

Disclosed is a distortion-compensation apparatus that can reduce the storage space for storing coefficients required for distortion-compensation calculation, and can accurately execute distortion compensation. Distortion-compensation apparatus ( 100 ) compensates for distortion of an output signal from a predetermined circuit by predistortion in which an input signal is preliminarily multiplied by a coefficient. First multiplication section ( 200 c ) of distortion-compensation apparatus ( 100 ) multiplies an input signal by a first coefficient selected from coefficient candidates in accordance with the input signal; second multiplication section ( 201 c 1 to 201 c m ) multiplies a delay signal of an input signal by a tap coefficient; and adding section ( 202 ) outputs a signal obtained by adding together an input signal multiplied by the compensation coefficient and the delay signal multiplied by the tap coefficient to the predetermined circuit.

Claims (14)

1. A distortion-compensation apparatus comprising:

a first multiplication section that obtains a first multiplication signal by multiplying an input signal by a first pre-distortion coefficient selected from a plurality of first coefficient candidates in accordance with the input signal;

a second multiplication section that obtains a second multiplication signal by multiplying a delay signal of the input signal by a second pre-distortion coefficient;

an adding section that obtains an addition signal by adding the first multiplication signal and the second multiplication signal and outputs the addition signal to a predetermined circuit; and

an update-processing section that updates the first pre-distortion coefficient and the second pre-distortion coefficient by convergence calculation using an iteration scheme based on the input signal and the output signal outputted from the predetermined circuit, wherein,

the update-processing section updates the first pre-distortion coefficient, then updates the second pre-distortion coefficient, and after then updates both of the first updated pre-distortion coefficient and the second updated pre-distortion coefficient.

2. The distortion-compensation apparatus according to claim 1 , wherein when an absolute value of the second updated pre-distortion coefficient is smaller than a predetermined threshold, the update-processing section excludes the second updated pre-distortion coefficient from the convergence calculation.

3. The distortion-compensation apparatus according to claim 1 , wherein the iteration scheme is a Least Mean Square scheme.

4. A distortion-compensation method comprising:

obtaining a first multiplication signal by multiplying an input signal by a first pre-distortion coefficient selected from a plurality of first coefficient candidates in accordance with the input signal;

obtaining a second multiplication signal by multiplying a delay signal of the input signal by a second pre-distortion coefficient;

obtaining an addition signal by adding the first multiplication signal and the second multiplication signal;

outputting the addition signal to a predetermined circuit; and

updating the first pre-distortion coefficient, then updating the second pre-distortion coefficient, and after then updating both of the first updated pre-distortion coefficient and the second updated pre-distortion coefficient by convergence calculation using an iteration scheme based on the input signal and the output signal outputted from the predetermined circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2015
From: HIRAI, YOSHITO; OKAMOTO, KOUJI
To: PANASONIC CORPORATION
Reel/Frame 036213/0409 →
Priority Claims (1)
JP 2012-282752 · Dec 26, 2012 · national
Continuity (1)
Related Publication 20150349725A1 · Dec 3, 2015