Reconfigurable processor and method for optimizing configuration memory

1. A method of optimizing use of a configuration memory of a reconfigurable processor, the method comprising:

analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and details of the configuration memory;

scheduling groups of function units (FUs), which will be activated in each cycle of the loop, according to the analyzed parallelism to generate configuration data of each cycle; and

sequentially mapping classification letters for classifying the generated configuration data and the groups with respect to the scheduled groups in adjacent cycles in at least one row of the configuration memory,

wherein the classification letters are mapped according to a determination of whether regular encoding of the configuration data is possible, based on the architecture and the details of the configuration memory,

wherein if the regular encoding is possible, the classification letters are mapped according to a determination of whether the groups are the same in the adjacent cycles,

wherein the configuration data is encoded regularly when the configuration data is mapped uniformly on fields of the configuration memory.

2. The method of claim 1 , wherein groups of different types of all FUs comprised in the reconfigurable processor are scheduled to be interleaved and activated in order to generate the configuration data.

3. The method of claim 1 , wherein the classification letters correspond to flag bits that are inserted between a plurality of fields classifying a storage area of the configuration memory.

4. The method of claim 3 , wherein the classification letters comprise a continue bit for identifying that the configuration data mapped in adjacent fields in the configuration memory is the same cycles and a stop bit for identifying that the configuration data mapped in adjacent fields in the configuration memory is not the same cycles.

5. The method of claim 1 , wherein the generated configuration data is mapped in the configuration memory by using regular encoding.

6. The method of claim 5 , wherein the configuration data respectively corresponding to the groups are regularly mapped to each of fields of the configuration memory.

7. The method of claim 1 ,

wherein if it is determined that the regular encoding is possible, and the groups are not the same, the generated configuration data and the classification letters are mapped in the configuration memory.

8. A non-transitory computer-readable recording medium having recorded thereon a program for executing the method of claim 1 in a computer.

9. An apparatus for optimizing use of a configuration memory of a reconfigurable processor, the apparatus comprising:

an analyzer which analyzes a parallelism of a loop of a program code based on an architecture of the reconfigurable processor and details of the configuration memory;

a scheduling unit which schedules groups of FUs, which will be activated in each cycle of the loop, according to the analyzed parallelism to generate configuration data of each cycle; and

a determiner which sequentially maps classification letters for classifying the generated configuration data and the groups with respect to the scheduled groups in adjacent cycles, in at least one row of the configuration memory,

wherein the determiner determines whether regular encoding of the configuration data is possible, based on the architecture and the details of the configuration memory,

wherein if the regular encoding is possible, the classification letters are mapped according to a determination of whether the groups are the same in the adjacent cycles,

wherein the configuration data is encoded regularly when the configuration data is mapped uniformly on fields of the configuration memory.

10. The apparatus of claim 9 , wherein the scheduling unit schedules groups of different types of all FUs comprised in the reconfigurable processor to interleave and activate the groups in order to generate the configuration data.

11. The apparatus of claim 9 , wherein the classification letters correspond to flag bits that are inserted between a plurality of fields classifying a storage area of the configuration memory.

12. The apparatus of claim 11 , wherein the classification letters comprise a continue bit for identifying that the configuration data mapped in adjacent fields in the configuration memory is the same cycles and a stop bit for identifying that the configuration data mapped in adjacent fields in the configuration memory is not the same cycles.

13. The apparatus of claim 9 , wherein the determiner maps the generated configuration data in the configuration memory by using regular encoding.

14. The apparatus of claim 13 , wherein the determiner classifies each of fields of the configuration memory to regularly map the configuration data respectively corresponding to the groups.

15. The apparatus of claim 9 , wherein, if it is determined that the regular encoding is possible, and the groups are not the same, the determiner maps the generated configuration data and the classification letters in the configuration memory.