Using a decrementer interrupt to start long-running hardware operations before the end of a shared processor dispatch cycle

1. A system comprising:

one or more shared computer processors; and

a memory containing a program, which when executed by the one or more shared computer processors, performs an operation comprising:

processing a plurality of logical partitions on a shared processor for the duration of a respective dispatch cycle;

issuing, by a hypervisor, at a predefined time prior to completion of each dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a respective cache line address buffer location in a virtual processor;

responsive to each lightweight HDEC interrupt, writing, by the shared processor, a set of cache line addresses used by each logical partition to the respective cache line address buffer location in the virtual processor;

determining an average amount of time required to write the sets of cache line addresses; and

setting the average amount of time as the predefined time to issue the lightweight HDEC during subsequent processing of each logical partition.

2. The system of claim 1 , the operation further comprising:

determining an amount of time required to write each of the set of cache line addresses to the respective cache line address buffer; and

storing each amount of time.

3. The system of claim 1 , the operation further comprising:

upon determining that a count of times the shared processor completes the writing of the sets of cache line addresses to the buffer prior to the completion of each respective dispatch cycle exceeds a predefined threshold, subtracting a fractional amount of time from the predefined time to cause the lightweight interrupt to be issued closer to the end of the dispatch cycle for the first logical partition.

4. The system of claim 1 , the operation further comprising:

upon determining that a count of times the shared processor completes the writing of the sets of cache line addresses to the buffer after the completion of each respective dispatch cycle exceeds a predefined threshold, adding a fractional amount of time to the predefined time to cause the lightweight interrupt to be issued occur further from the end of the dispatch cycle for the first logical partition.

5. The system of claim 1 , the operation further comprising:

upon completion of the dispatch cycle for the first logical partition, issuing, by the hypervisor, a hypervisor decrementer (HDEC) interrupt that causes a second logical partition to be processed by the shared processor for the duration of a next dispatch cycle.

6. The system of claim 1 , wherein the cache line addresses are written to the cache line address buffer in order to facilitate a subsequent micropartition prefetch process by the first logical partition.

7. A computer program product, comprising:

a non-transitory computer-readable storage medium having computer-readable code embodied therewith, the computer-readable program code executable by a shared processor to perform an operation comprising:

processing a plurality of logical partitions on a shared processor for the duration of a respective dispatch cycle;

issuing, by a hypervisor, at a predefined time prior to completion of each dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a respective cache line address buffer location in a virtual processor;

responsive to each lightweight HDEC interrupt, writing, by the shared processor, a set of cache line addresses used by each logical partition to the respective cache line address buffer location in the virtual processor;

determining an average amount of time required to write the sets of cache line addresses; and

setting the average amount of time as the predefined time to issue the lightweight HDEC during subsequent processing of each logical partition.

8. The computer program product of claim 7 , further comprising:

determining an amount of time required to write each of the set of cache line addresses to the respective cache line address buffer; and

storing each amount of time.

9. The computer program product of claim 7 , the operation further comprising:

upon determining that a count of times the shared processor completes the writing of the sets of cache line addresses to the buffer prior to the completion of each respective dispatch cycle exceeds a predefined threshold, subtracting a fractional amount of time from the predefined time to cause the lightweight interrupt to be issued closer to the end of the dispatch cycle for the first logical partition.

10. The computer program product of claim 7 , the operation further comprising:

upon determining that a count of times the shared processor completes the writing of the sets of cache line addresses to the buffer after the completion of each respective dispatch cycle exceeds a predefined threshold, adding a fractional amount of time to the predefined time to cause the lightweight interrupt to be issued occur further from the end of the dispatch cycle for the first logical partition.

11. The computer program product of claim 7 , the operation further comprising:

upon completion of the dispatch cycle for the first logical partition, issuing, by the hypervisor, a hypervisor decrementer (HDEC) interrupt that causes a second logical partition to be processed by the shared processor for the duration of a next dispatch cycle.

12. A computer program product, comprising:

a computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable a shared processor to perform an operation comprising:

processing a first logical partition on the shared processor for the duration of a dispatch cycle;

issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor; and

responsive to the lightweight HDEC interrupt, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor, wherein the cache line addresses are written to the cache line address buffer in order to facilitate a subsequent micropartition prefetch process by the first logical partition.

13. The computer program product of claim 12 , wherein the shared processor writes a set of cache line addresses for each of a plurality of logical partitions, the operation further comprising:

averaging the amounts of time required to write the set of cache line addresses for each of the plurality of logical partitions; and

setting the averaged amount of time as the predefined time to issue the lightweight HDEC interrupt during the processing of the first logical partition.