Threshold voltage grouping of memory cells in same threshold voltage range
A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.
1. A memory device, comprising:
a memory array including a plurality of bit lines and a plurality of memory cells storing a same data value;
a plurality of memory access circuits coupled to the plurality of bit lines in the memory array, the plurality of bit lines coupled to the plurality of memory cells, the plurality of memory access circuits including a plurality of sense nodes selectively coupled to the plurality of bit lines to read and program data via the plurality of bit lines; and
control circuitry programming the plurality of memory cells, the plurality of memory cells storing the same data value prior to said programming by the control circuitry, said programming by the control circuitry including:
regarding the plurality of memory cells occupying a first threshold voltage range, characterizing memory cells in the plurality of memory cells as belonging to particular threshold voltage subranges in a plurality of threshold voltage subranges that divide the first threshold voltage range;
storing the particular threshold voltage subranges in the plurality of threshold voltage subranges, to which the memory cells in the plurality of memory cells belong, in memory coupled to the plurality of memory access circuits; and
applying programming pulses to program the plurality of memory cells, the programming pulses having magnitudes that vary depending on the particular threshold voltage subranges in the plurality of threshold voltage subranges to which the memory cells in the plurality of memory cells belong.
2. The device of claim 1 , wherein said programming by the control circuitry includes:
prior to said characterizing the memory cells and prior to said applying the programming pulses, applying no early programming pulses to the plurality of memory cells.
3. The device of claim 1 ,
wherein said programming by the control circuitry includes:
storing respective target threshold voltage ranges of the plurality of memory cells in the plurality of memory access circuits.
4. The device of claim 1 , wherein said magnitudes of the programming pulses also depend on respective target threshold voltage ranges of the memory cells in the plurality of memory cells.
5. The device of claim 4 , wherein one or more program verify periods of one or more target threshold voltage ranges are skipped, responsive to said one or more program verify periods not characterizing any of the plurality of memory cells.
6. The device of claim 4 , wherein said programming pulses are divided into a plurality of discrete programming periods dedicated to a plurality of combinations of the plurality of threshold voltage subranges and the respective target threshold voltage ranges.
7. The device of claim 1 , wherein memory cells of the plurality of memory cells have a same target threshold voltage range.
8. The device of claim 1 , wherein memory cells of the plurality of memory cells have different target threshold voltage ranges.
9. A memory device, comprising:
a memory array including a plurality of bit lines and a plurality of memory cells storing a same data value; and
control circuitry programming the plurality of memory cells, the plurality of memory cells storing the same data value prior to said programming by the control circuitry, said programming by the control circuitry including:
regarding the plurality of memory cells occupying a first threshold voltage range, characterizing memory cells in the plurality of memory cells as belonging to particular threshold voltage subranges in a plurality of threshold voltage subranges that divide the first threshold voltage range; and
applying programming pulses to program the plurality of memory cells, the programming pulses having magnitudes that vary depending on the particular threshold voltage subranges in the plurality of threshold voltage subranges to which the memory cells in the plurality of memory cells belong, wherein said programming by the control circuitry includes:
prior to said characterizing the memory cells and prior to said applying the programming pulses, applying at least one early programming pulse to the plurality of memory cells to establish threshold voltages in said first threshold voltage range.
10. The device of claim 9 ,
further comprising:
a plurality of memory access circuits coupled to a plurality of bit lines in the memory array, the plurality of bit lines coupled to the plurality of memory cells, the plurality of memory access circuits including a plurality of sense nodes selectively coupled to the plurality of bit lines to read and program data via the plurality of bit lines,
wherein said programming by the control circuitry includes:
storing the particular threshold voltage subranges in the plurality of threshold voltage subranges to which the memory cells in the plurality of memory cells belong in the plurality of memory access circuits.
11. The device of claim 9 ,
wherein said programming by the control circuitry includes:
prior to said characterizing, characterizing an upper boundary of the first threshold voltage range.
12. The device of claim 9 ,
wherein said programming by the control circuitry includes:
prior to said characterizing, characterizing a lower boundary of the first threshold voltage range.
13. The device of claim 9 ,
wherein said programming by the control circuitry includes:
prior to said characterizing, characterizing a peak of the first threshold voltage range.
14. A method of programming memory, comprising:
receiving a program instruction at an integrated circuit to program a plurality of memory cells storing a same data value; then
regarding the plurality of memory cells occupying a first threshold voltage range, characterizing memory cells in the plurality of memory cells as belonging to particular threshold voltage subranges in a plurality of threshold voltage subranges that divide the first threshold voltage range;
storing the particular threshold voltage subranges in the plurality of threshold voltage subranges to which the memory cells in the plurality of memory cells belong; and then
applying programming pulses to program the plurality of memory cells, the programming pulses having magnitudes that vary depending on the stored particular threshold voltage subranges in the plurality of threshold voltage subranges to which the memory cells in the plurality of memory cells belong.
15. The method of claim 14 , further comprising:
prior to said characterizing, applying at least one early programming pulse to the plurality of memory cells to establish threshold voltages in said first threshold voltage range; and characterizing an upper boundary of the first threshold voltage range.
16. The method of claim 14 , further comprising:
prior to said characterizing, applying at least one early programming pulse to the plurality of memory cells to establish threshold voltages in said first threshold voltage range; and characterizing a lower boundary of the first threshold voltage range.
17. The method of claim 14 , wherein said magnitudes of the programming pulses also depend on respective target threshold voltage ranges of the memory cells in the plurality of memory cells.
18. The method of claim 17 , wherein one or more program verify periods of one or more target threshold voltage ranges are skipped, responsive to said one or more program verify periods not characterizing any of the plurality of memory cells.
19. The method of claim 17 , wherein said programming pulses are divided into a plurality of discrete programming periods dedicated to a plurality of combinations of the plurality of threshold voltage subranges and the respective target threshold voltage ranges.
20. A memory device, comprising:
a memory array including a plurality of bit lines and a plurality of memory cells storing a same data value; and
control circuitry programming the plurality of memory cells, the plurality of memory cells storing the same data value prior to said programming by the control circuitry, said programming by the control circuitry including:
regarding the plurality of memory cells occupying a first threshold voltage range, characterizing memory cells in the plurality of memory cells as belonging to particular threshold voltage subranges in a plurality of threshold voltage subranges that divide the first threshold voltage range; and
applying programming pulses to program the plurality of memory cells, the programming pulses having magnitudes that vary depending on the particular threshold voltage subranges in the plurality of threshold voltage subranges to which the memory cells in the plurality of memory cells belong,
wherein consecutive programming pulses are applied between any two adjacent program verify pulses.