Semiconductor devices and fabricating methods thereof

1. A semiconductor device comprising:

a first fin on a substrate;

a field insulating layer disposed on portion of sidewalls of the first fin and on the substrate;

an interlayer dielectric layer on the field insulating layer and including a trench exposing at least a portion of the field insulating layer;

a spacer on a sidewall of the trench;

a deposition insulating layer on the spacer in the trench and on the portion of the field insulating layer;

a gate insulating layer in the trench and on the deposition insulating layer therein; and

a metal gate on the gate insulating layer in the trench,

wherein a first height from a top surface of the first fin to a top surface of the metal gate is smaller than a second height from the field insulating layer to the top surface of the first fin.

2. The semiconductor device of claim 1 , wherein the deposition insulating layer is conformally formed along sidewalls and a bottom surface of the trench.

3. The semiconductor device of claim 1 , wherein the deposition insulating layer is formed only on the bottom surface of the trench.

4. The semiconductor device of claim 1 , wherein the gate insulating layer is conformally formed along sidewalls and a bottom surface of the trench.

5. The semiconductor device of claim 1 , wherein the metal gate includes a work function control film conformally formed along sidewalls and a bottom surface of the trench.

6. The semiconductor device of claim 1 , wherein the substrate is a group III-V substrate.

7. The semiconductor device of claim 1 , wherein a channel of the metal gate includes a SiGe channel.

8. A semiconductor device comprising:

a first fm and a second fin on a substrate lengthwise to be parallel to each other;

a field insulating layer between the first fin and the second fin on the substrate;

an interlayer dielectric layer on the first fin, the second fin and the field insulating layer and including a first trench that exposes a portion of the first fin and a second trench that exposes a portion of the field insulating layer;

a first gate in the first trench; and

a deposition insulating layer in the second trench on the field insulating layer;

a gate insulating layer in the second trench on the deposition insulating layer; and

a dummy gate in the second trench on the gate insulating layer,

wherein a first height from a top surface of the first fin to a top surface of the first gate is smaller than a second height from the field insulating layer to the top surface of the first fin.

9. The semiconductor device of claim 8 , wherein a top surface of the field insulating layer is lower than a top surface of the first fin.

10. The semiconductor device of claim 9 ,

wherein a first spacer and a second spacer are disposed on both sidewalls of the dummy gate,

wherein sidewalls of the first spacer and the first fin are spaced apart from each other, and

wherein sidewalls of the second spacer and the second fin are spaced apart from each other.

11. The semiconductor device of claim 8 , further comprising a first elevated source/drain in the first fin at opposite sides of the first gate.

12. The semiconductor device of claim 8 ,

the deposition insulating layer in the second trench to be disposed on a portion of sidewalls of the first fin.

13. The semiconductor device of claim 12 , wherein the deposition insulating layer extends up to a top surface of the first fin.

14. A semiconductor device comprising:

a field insulating layer;

an active region defined by the field insulating layer and including a first fin; and

gate structures extending lengthwise on the field insulating layer and the active region and including multiple functional layers stacked thereon,

wherein a stacking order of the multiple functional layers of the gate structure on the field insulating layer and a stacking order of the multiple functional layers of the gate structure on the active region are the same,

wherein the gate structure comprises a spacer, a deposition insulating layer on the spacer, a gate insulating layer on the deposition insulating layer, and a metal gate on the gate insulating layer, and

wherein a first height from a top surface of the first fin to a top surface of the gate structures is smaller than a second height from the field inslating layer to the top surface of the first fin.

15. The semiconductor device of claim 1 , wherein the spacer and the gate insulating layer are spaced apart each other.

16. The semiconductor device of claim 14 , wherein the spacer and the gate insulating layer are spaced apart each other.

17. The semiconductor device of claim 8 , further comprising a second deposition insulating layer conformally formed in the first trench under the first gate.

18. The semiconductor device of claim 17 , further comprising a second gate insulating layer between the second deposition insulating layer and the first gate.

19. The semiconductor device of claim 8 , wherein the first gate includes a work function control film conformally formed along sidewalls and a bottom surface of the trench.

20. The semiconductor device of claim 14 , wherein the deposition insulating layer is conformally formed on the spacer and the active region.

21. The semiconductor device of claim 14 , wherein the gate insulating layer is conformally formed on the deposition insulating layer.

22. The semiconductor device of claim 14 , wherein the metal gate includes a work function control film conformally formed on the gate insulating layer.

23. The semiconductor device of claim 14 , wherein the substrate is a group III-V substrate.